MC68LC302 PRODUCT INFORMATION
MC68LC302 APPLICATIONS
The MC68LC302 excels in several applications areas.
First, any application using the MC68302,but not needing all three serial channels is a potential candidate for
the MC68LC302. Note however, that the MC68LC302 sacrifices most of the provision for external bus
mastership, thus the MC68LC302 may not be appropriate where the MC68302 is used as part of larger
systems.
Second, the MC68LC302 excels in low power and portable applications. The inclusion of a static 68000 core,
coupled with the low power modes built into the device make it ideal for handheld, or other low power
applications. The new 32 kHz or 4 MHz PLL option greatly reduces the total power budget of the designer’s
board, and allows the MC68LC302 to be an effective device in low power systems. The MC68LC302 can then
optionally generate a full frequency clock for use by the rest of the board. During low power modes, the new
periodic interrupt timer (PIT) allows the device to awaken at regular intervals. In addition, two pins can awaken
the device from low power modes.
Third, given that the MC68LC302 is packaged in a 100TQFP package, it allows the MC68LC302 to be used
in space critical applications, as well as height critical applications such as PCMCIA cards.
Fourth, since the disable CPU mode (also known as slave mode) is still retained, the MC68LC302 can function
as a fully intelligent DMA-driven peripheral chip containing serial channels, timers, chip selects, etc.
DIFFERENCES BETWEEN THE MC68LC302 AND MC68302
The MC68LC302 has some specific differences from the MC68302. Even though the functionality of the
processor and the peripherals remain the same, some of the flexibility has been removed due to the pin
reduction from 132 on the original MC68302, to 100 pins on the MC68LC302.
The following features have been removed or modified from the MC68302 in order to make the MC68LC302
possible.
• SCC3 and its baud rate generator (BRG3) are removed.
• External masters are not able to take the bus away from the MC68LC302 through the normal bus arbi-
tration scheme as these pins no longer exist. An external master can still maintain bus mastership
through a simple scheme using the HALT
pin. This restriction does not apply when using the MC68LC302
in CPU disabled mode (slave mode), in which case BR, BG, and BGACK are all available.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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