Enpirion
®
Power Evaluation Board User Guide
EN5364QI PowerSoC
o Parallel Mode operation – Up to 4 EN5364QI devices may be
operated in parallel when load currents greater than 6A is desired.
In parallel mode, one device is designated the Master and up to 3
devices operate in slave mode, controlled by the Master. The PWM
output of the Master is routed to slave devices. By daisy chaining
the Slave devices even more devices can be operated in parallel
but practical considerations, such as board layout would limit the
number of slave devices to three.
o Soft-Start – A 15nF (C11) soft-start capacitor is populated on the
evaluation board for an output voltage ramp time of ~1ms. This may
be swapped for a different value capacitor if a different ramp time is
desired. To limit the inrush current this capacitor value should be
greater than 4.7nF. The output voltage rise time is ~65k*C
SS
.
• The EN5364QI features a customer programmable output voltage by
means of a resistor divider. The resistor divider allows the user to set the
V
OUT
to any value within the range 0.6V to approximately (V
IN
-0.5V).
`Referring to Figure 1, the evaluation board, as shipped is populated with
a single R
A
, a single C
A
, and four possible R
B
resistors. A jumper selects
one of the 4 R
B
resistors to produce a voltage of 0.804, 0.998, 1.2 or
1.8Volts. You can populate more than one R
B
jumper position to get even
higher output voltages. See “VOUT Programming” section in the
evaluation board schematic (Figure 7).
• The EN5364QI includes the bulk of the compensation network internally.
However, an external phase-lead (zero) capacitor is required as part of the
feedback. This network is shown in Figure -1. Appropriate component
values allow for optimum compensation for a given Input voltage and
choice of loop bandwidth. The equations in Figure 1 provide the details to
calculate component values.
• MAR1 and MAR2 are ternary input signals. The pins are allowed to be in a
low state (tied to GND), a high state (tied to V
IN
), or a float state. Table-1
shows the margining truth table. Accordingly, the output voltage can be
nominal or ±2.5%, ±5% or ±10% about the nominal. 7 out of 9 possible
states of MAR[1:2] are used for margining. The other two states are
reserved for diagnostics. If tying MAR[1,2] to V
IN
, a series resistor is
recommended to reduce the pin input current (see Figure 2).
• A footprint is provided for a SMC connector (not populated) for S_IN. A
clock source (3.6 to 4.4MHz) may be applied to S_IN to synchronize the
device switching frequency to the external source. S_OUT will output a
clock signal synchronous with the switching frequency, with a phase
delay. S_OUT of one EN5364QI may be connected to S_IN of another
EN5364QI device in different modes of operation.
• The phase delay is set by connecting a resistor from S_delay to AGND.
The delay is approximately:
Delay (nsec) = 2*[S_delay resistance in k
.]
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