© 2014 Exar Corporation
XR81102
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Rev 1B
Application Information
Termination for LVPECL Outputs
The termination schemes shown in Figure 2 and Figure 3
are typical for LVPECL outputs. Matched impedance layout
techniques should be used for the LVPECL output pairs to
minimize any distortion that could impact your maximum
operating frequency. Figure 4 is an alternate termination
scheme that uses a Y-termination approach.
Figure 2: XR81102 3.3V LVPECL Output Termination
Figure 3: XR81102 2.5V LVPECL Output Termination
Figure 4: XR81102 Alternate LVPECL Output Termination
Using Y-termination
Output Signal Timing Definitions
The following diagrams clarify the common definitions of
the AC timing measurements.
Figure 5: Cycle-to-Cycle Jitter
Figure 6: Output Rise/Fall Time and Swing
Figure 7: Output Period and Duty Cycle
