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CS4361-CZZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
7
CS4361
Confidential Draft
9/30/11
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam-
ple rate by multiplying the given characteristic by Fs. (See Note 5)
2. Response is clock-dependent and will scale with Fs.
3. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
For Quad-Speed Mode, the measurement bandwidth is 0.7 Fs to 1 Fs.
4. De-emphasis is available only in Single-Speed Mode.
5. Amplitude vs. Frequency plots of this data are available in “Performance Plots” on page 18.
Parameter Symbol Min Typ Max Unit
Single-Speed Mode
Passband (Note 2) to -0.05 dB corner
to -3 dB corner
0
0
-
-
.4780
.4996
Fs
Fs
Frequency Response 10 Hz to 20 kHz -.01 - +.08 dB
StopBand .5465 - - Fs
StopBand Attenuation (Note 3) 50 - - dB
Group Delay tgd - 10/Fs - s
De-emphasis Error (Note 4) Fs = 44.1 kHz - - +.05/-.25 dB
Double-Speed Mode
Passband (Note 2) to -0.1 dB corner
to -3 dB corner
0
0
-
-
.4650
.4982
Fs
Fs
Frequency Response 10 Hz to 20 kHz -.05 - +.2 dB
StopBand .5770 - - Fs
StopBand Attenuation (Note 3) 55 - - dB
Group Delay tgd - 5/Fs - s
Quad-Speed Mode
Passband (Note 2) to -0.1 dB corner
to -3 dB corner
0
0
-
-
0.397
0.476
Fs
Fs
Frequency Response 10 Hz to 20 kHz 0 - +0.00004 dB
StopBand 0.7 - - Fs
StopBand Attenuation (Note 3) 51 - - dB
Group Delay tgd - 2.5/Fs - s
8
CS4361
Confidential Draft
9/30/11
DIGITAL INPUT CHARACTERISTICS
6. RST pin has an input threshold relative to VL, but is VA tolerant.
7. I
in
for LRCK is ±20 A max.
POWER & THERMAL CHARACTERISTICS
8. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are
based on highest FS and highest MCLK. Current variance between speed modes is small.
9. Power-Down Mode is defined when all clock and data lines are held static.
10. Valid with the recommended capacitor values on VQ and FILT+
as shown in the typical connection di-
agram in Section 4.
Parameters Symbol Min Typ Max Units
High-Level Input Voltage -all input Pins except RST (% of VL) V
IH
70% - - V
Low-Level Input Voltage -all input Pins except RST (% of VL) V
IL
- - 30% V
High-Level Input Voltage -RST pin (Note 6) (% of VL) V
IH
90% - - V
Low-Level Input Voltage -RST pin (% of VL) V
IL
- - 10% V
Input Leakage Current (Note 7) I
in
--±10A
Input Capacitance - 8 - pF
Parameters Symbol
5V Nom
Units
Min Typ Max
Power Supplies
Power Supply Current normal operation
(Note 8)
power-down state (Note 9)
I
A
I
L
I
A
I
L
-
-
-
-
66
0.1
300
26
90
1
-
-
mA
mA
A
A
Power Dissipation normal operation
power-down state (Note 9)
-
-
331
1.63
455
-
mW
mW
Package Thermal Resistance
JA
-72-°C/Watt
Power Supply Rejection Ratio (Note 10) (1 kHz)
(60 Hz)
PSRR -
-
60
40
-
-
dB
dB
AOUTx
AGND
3.3 µF
V
out
R
L
C
L
Figure 1. Equivalent Output Test Load Figure 2. Maximum Loading
100
50
75
25
2.5
51015
Safe Operating
Region
Capacitive Load -- C (pF)
L
Resistive Load -- R (k
)
L
125
3
20
9
CS4361
Confidential Draft
9/30/11
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE
11. Not all sample rates are supported for all clock ratios. See table “Common Clock Frequencies” on
page 12 for supported ratios and frequencies.
12. In Internal SCLK Mode, the duty cycle must be 50%
±1/2 MCLK period.
13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on data format and
MCLK/LRCK ratio. (See Figures 7-10)
Parameters Symbol Min Typ Max Units
MCLK Frequency 0.512 - 50 MHz
MCLK Duty Cycle 45 - 55 %
Input Sample Rate All MCLK/LRCK ratios combined
(Note 11) 256x, 384x, 1024x
256x, 384x
512x, 768x
1152x
128x, 192x
64x, 96x
128x, 192x
Fs 2
2
84
42
30
50
100
168
216
54
134
67
34
108
216
216
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
External SCLK Mode
LRCK Duty Cycle (External SCLK only) 45 50 55 %
SCLK Pulse Width Low t
sclkl
20 - - ns
SCLK Pulse Width High t
sclkh
20 - - ns
SCLK Duty Cycle 45 50 55 %
SCLK rising to LRCK edge delay t
slrd
20 - - ns
SCLK rising to LRCK edge setup time t
slrs
20 - - ns
SDIN valid to SCLK rising setup time t
sdlrs
20 - - ns
SCLK rising to SDIN hold time t
sdh
20 - - ns
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only) (Note 12) -50-%
SCLK Period (Note 13)
t
sclkw
--ns
SCLK rising to LRCK edge
t
sclkr
--s
SDIN valid to SCLK rising setup time
t
sdlrs
--ns
SCLK rising to SDIN hold time
MCLK / LRCK =1152, 1024, 512, 256, 128, or 64
t
sdh
--ns
SCLK rising to SDIN hold time
MCLK / LRCK = 768, 384, 192, or 96
t
sdh
--ns
tsclkw
2
------------------
10
9
512Fs
----------------------10+
10
9
512Fs
----------------------15+
10
9
384Fs
----------------------15+
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

CS4361-CZZ

Mfr. #:
Buy CS4361-CZZ
Manufacturer:
Cirrus Logic
Description:
Audio D/A Converter ICs 6-Ch DAC 24-Bit 192kHz 105dB
Lifecycle:
New from this manufacturer.
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