• Security block for implementing
crypto algorithms
• RapidIO message manager, which allows
Type9 and Type11 packets to connect
directly with DPAA infrastructure
• Pattern matching engine to search for
text strings in packets for unified threat
management
The DPAA achieves near-linear scaling as
additional cores are applied to a task.
CoreNet Switch Fabric
The fabric-based interface provides scalable
on-chip, point-to-point connectivity supporting
concurrent traffic to and from multiple
resources connected to the fabric, eliminating
single-point bottlenecks for non-competing
resources. This is designed to eliminate bus
contention and latency issues associated
with scaling shared bus architectures that are
common in other multicore approaches.
Secure Boot
The secure boot feature ensures that the
P2040 and P2041 processors only run
authenticated code. Through a set of fuses
that OEMs can program once but can never
be read, secure boot prevents unauthorized
parties from reverse engineering code to steal
intellectual property, from loading illegitimate
code to change system functionality or from
extracting sensitive user information that may
be stored in the system.
Target Applications
The P2040 and P2041 processors are
targeted at mixed control plane and data plane
applications, where in previous generations,
separate devices would implement each
function. Typically, one or two cores would
implement the control plane, while the
remaining cores implement the data plane.
The hardware hypervisor facilitates this, with
its capability to safely provision flexible core
allocations into groups running SMP, one
core running alone, separate cores running in
parallel or a core running end-user applications.
With over a 2x performance range in a single
package, the P2040 and P2041 processors
together allow customers to use bill of
materials stuffing options in a single board
to develop a range of products at different
performance and price points. For instance, the
P2040 processor addresses the fixed router
and the P2041 processor the modular router.
The P2040 may address the LTE channel
card while the P2041 addresses the network
interface card. Other applications include UTM,
aerospace and defense, multi-function printers
and factory automation.
Software and Tools Support
• Enea
®
: Real-time operating system support
• Green Hills
®
: Complete portfolio of software
and hardware development tools, trace
tools and real-time operating systems
• Mentor Graphics
®
: Commercial-grade
Linux
®
solution
• CodeSourcery: GCC and GDB tool chain
• P2040 and P2041 reference design
board (RDB)
For more information, visit freescale.com/QorIQ
Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. CoreNet is a
trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power
Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks
licensed by Power.org. © 2011, 2013 Freescale Semiconductor, Inc.
Document Number: QP2040FS REV 3
QorIQ P2040/P2041 Features List
Four e500mc cores, built on
Power Architecture
®
technology
• 4x e500mc cores (P2040: up to 1.2 GHz; P2041: up to 1.5 GHz)
• 32 KB L1-I cache and 32 KB L1-D cache per core
• 128 KB L2 cache per core (P2041 only)
Memory controller • DDR3/3L up to 1.2 GHz (P2040) and 1.33 GHz (P2041)
• 32/64-bit data bus w/ECC
High-Speed interconnects • 10 x 5 GHz SerDes lanes
• 3 x PCI Express 2.0 controllers
• 2 x Serial RapidIO 1.3/2.1 controllers
• 2 x SATA 2.0 at 3 GB/s
CoreNet switch fabric • 1 MB CoreNet platform cache with ECC
• Peripheral access management unit (PAMU) controls external device
access to memory space
Ethernet • One 10-Gigabit Ethernet (XAUI) controller (P2041 only)
• Up to 5x SGMII, 4x 2.5 GB/s SGMII, 2x RGMII
• All with classification, hardware queueing, policing, buffer management,
checksum offload, QoS, lossless flow control, IEEE
®
1588
Data path acceleration • SEC 4.2: Public key accelerator, DES, AES, message digest accelerator,
random number generator, ARC4, SNOW 3G F8 and F9, CRC, Kasumi
• PME 2.1: Searches for 128 byte text strings in 32 KB patterns in 128
million sessions
• RapidIO messaging: Type 9 and 11
Additional peripheral interfaces • SD/MMC
• SPI controller
• Four I
2
C controllers
• 2x USB 2.0 with PHY
• Two dual UARTs
• Enhanced local bus controller (eLBC), 16-bit
Device • 45 nm SOI process technology
• 783-pin FCPBGA package, 23 x 23 mm
