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MAX4685EUB

P1-P3P4-P6P7-P9P10-P10
UCSP Package Consideration
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note (Wafer-Level Ultra-Chip-Board-Scale Package).
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
Chip Information
PROCESS: BiCMOS
MAX4684/MAX4685
0.5
ΩΩ
/0.8
ΩΩ
Low-Voltage, Dual SPDT
Analog Switches in UCSP
_______________________________________________________________________________________ 7
t
r
< 5ns
t
f
< 5ns
50%
V
IL
LOGIC
INPUT
R
L
50Ω
COM_
GND
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
N_ (
R
L
)
R
L
+ R
ON
V
IN_
V
IH
t
OFF
0
NO_
OR NC
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
C
L
35pF
V+
V
OUT
MAX4684
MAX4685
Figure 2. Switching Time
Test Circuits/Timing Diagrams
50%
V
IH
V
IL
LOGIC
INPUT
V
OUT
0.9 x V
OUT
t
D
LOGIC
INPUT
R
L
50Ω
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
V
OUT
V+
V+
C
L
35pF
V
N_
COM_
MAX4684
MAX4685
Figure 3. Break-Before-Make Interval
MAX4684/MAX4685
0.5
ΩΩ
/0.8
ΩΩ
Low-Voltage, Dual SPDT
Analog Switches in UCSP
8 _______________________________________________________________________________________
V
GEN
GND
COM_
C
L
V
OUT
V+
V
OUT
IN
OFF
ON
OFF
ΔV
OUT
Q = (ΔV
OUT
)(C
L
)
NC_
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
V
IL
TO V
IH
V+
R
GEN
IN_
MAX4684
MAX4685
OR NO_
Figure 4. Charge Injection
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO ALL OTHER CHANNELS.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
+5V
V
OUT
V+
IN_
NC_
COM
NO
V
IN
MAX4684
MAX4685
OFF-ISOLATION = 20log
V
OUT
V
IN
ON-LOSS = 20log
V
OUT
V
IN
CROSSTALK = 20log
V
OUT
V
IN
NETWORK
ANALYZER
50Ω
50Ω 50Ω
50Ω
MEAS REF
10nF
0V OR V+
50Ω
GND
Figure 5. On-Loss, Off-Isolation, and Crosstalk
CAPACITANCE
METER
NC_ or
NO_
COM_
GND
IN
V
IL
OR
V
IH
10nF
V+
f = 1MHz
V+
MAX4684
MAX4685
Figure 6. Channel Off/On-Capacitance
Test Circuits/Timing Diagrams (continued)
TOP VIEW
NC2
IN1
GND
NC1
COM2
IN2
COM1
NO1
NO2
V+
3mm
✕
3mm TDFN
9
8
10
7
6
*CONNECT EP TO GND.
2
3
1
4
5
*EP
MAX4684/MAX4685
Pin Configurations (continued)
MAX4684/MAX4685
0.5
ΩΩ
/0.8
ΩΩ
Low-Voltage, Dual SPDT
Analog Switches in UCSP
_______________________________________________________________________________________ 9
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
12 UCSP B12-4
21-0104
10 TDFN-EP T1033-1
21-0137
10 µMAX U10-2
21-0061
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
P1-P3P4-P6P7-P9P10-P10

MAX4685EUB

Mfr. #:
Buy MAX4685EUB
Manufacturer:
Maxim Integrated
Description:
Analog Switch ICs 0.5Ohm/0.8Ohm Low-Voltage, Dual SPDT Analog Switches in UCSP
Lifecycle:
New from this manufacturer.
Delivery:
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