GS2961AIBE3 Datasheet GS2961AIBE3 | P1-P3

1 of 4GS2961A 3Gb/s, HD, SD SDI Receiver, with Integrated

Adaptive Cable Equalizer

Product Brief

55975 - A September 2010

GS2961A 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer

www.gennum.com

Key Features

• Operation at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s,

1.485/1.001Gb/s and 270Mb/s

• Supports SMPTE 425M (Level A and Level B), SMPTE

424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI

• Integrated adaptive cable equalizer

• Typical equalized length of Belden 1694A cable:

 150m at 2.97Gb/s

 250m at 1.485Gb/s

 480m at 270Mb/s

• Integrated Reclocker with low phase noise, integrated

VCO

• Serial digital reclocked, or non-reclocked output

• Ancillary data extraction

• Optional conversion from SMPTE 425M Level B to

Level A for 1080p 50/60 4:2:2 10-bit

• Parallel data bus selectable as either 20-bit or 10-bit

• Comprehensive error detection and correction

features

• Output H, V, F or CEA 861 Timing Signals

• 1.2V digital core power supply, 1.2V and 3.3V analog

power supplies, and selectable 1.8V or 3.3V I/O power

supply

• GSPI Host Interface

• Wide temperature range of -40ºC to +85ºC

• Low power operation (typically 515mW)

• Small 11mm x 11mm 100-ball BGA package

• Pb-free and RoHS compliant

Applications

Description

The GS2961A is a multi-rate SDI integrated Receiver which

includes complete SMPTE processing, as per SMPTE 425M,

292M and SMPTE 259M-C. The SMPTE processing features

can be bypassed to support signals with other coding

schemes.

The GS2961A integrates Gennum's adaptive cable

equalizer technology, achieving unprecedented cable

lengths and jitter tolerance. It features DC restoration to

compensate for the DC content of SMPTE pathological

signals.

The device features an Integrated Reclocker with an

internal VCO and a wide Input Jitter Tolerance (IJT) of

0.7UI.

HD-SDI

Application: Single Link (3G-SDI)

to Dual Link (HD-SDI) Converter

GS2962

Link A

Link B

HV F/PCLK

10-bit

3G-SDI

GS2961A

GS2962

10-bit

HV F/PCLK

HD-SDI

Application: Dual Link (HD-SDI)

to Single Link (3G-SDI) Converter

HD-SDI

Deserializer

GS2961A

Link A

FIFO

Deserializer

Link B

FIFO

GS2962

GS4910

10-bit

3G-SDI

HVF

XTAL

HV F/PCLK

GS2961A

10-bit

HD-SDI

2 of 4

GS2961A 3Gb/s, HD, SD SDI Receiver, with Integrated

Adaptive Cable Equalizer

Product Brief

55975 - A September 2010

A serial digital loop through output is provided, which can

be configured to output either reclocked or non-reclocked

serial digital data. The serial digital output can be connected

to an external cable driver.

The device operates in one of four basic modes: SMPTE

mode, DVB-ASI mode, Data-Through mode or Standby

mode.

In SMPTE mode (the default operating mode), the GS2961A

performs full SMPTE processing, and features a number of

data integrity checks and measurement capabilities.

The device also supports ancillary data extraction, and can

provide entire ancillary data packets through

host-accessible registers. It also provides a variety of other

packet detection and error handling features. All of these

processing features are optional, and may be individually

enabled or disabled through register programming.

Both SMPTE 425M Level A and Level B inputs are supported

with optional conversion from Level B to Level A for 1080p

50/59.94/60 4:2:2 10-bit inputs.

In DVB-ASI mode, sync word detection, alignment and

8b/10b decoding is applied to the received data stream.

In Data-Through mode all forms of SMPTE and DVB-ASI

processing are disabled, and the device can be used as a

simple serial to parallel converter.

The device can also operate in a lower power Standby

mode. In this mode, no signal processing is carried out and

the parallel output is held static.

Parallel data outputs are provided in 20-bit or 10-bit format

for 3Gb/s, HD and SD video rates, with a variety of mapping

options. As such, this parallel bus can interface directly with

video processor ICs, and output data can be multiplexed

onto 10 bits for a low pin count interface.

Functional Block Diagram

GS2961A Functional Block Diagram

Buffer Mux

Reclocker

with

Integrated

VCO

SDI

SDO

Serial

Parallel

Converter

Descramble,

Word Align,

Rate Detect

Flywheel

Video

Standard

Detect

TRS

Detect

Timing

Extraction

Mux

DVB-ASI

Decoder

Illegal code

remap,

TRS/

Line Number/

CRS

Insertion,

EDH Packet

Insertion

V/VSync

H/HSync

F/De

Rate_det[1:0]

ANC/

Checksum

/352M

Extraction

Error Flags

YANC/CANC

LOCKED

DVB_ASI

STANDBY

GSPI and

JTAG Controller

Host

Interface

Output Mux/

Demux

Crystal

Buffer/

Oscillator

LB_CONT

VBG

RC_BYP

I/O Control

TIM861

20BIT/10BIT

SMPTE_BYPASS

IOPROC_EN/DIS

RESET_TRST

CORE_VDD

CORE_GND

IO_VDD

IO_GND

SDO_EN/DIS

CS_TMS

SCLK_TCLK

SDIN_TDI

SDOUT_TDO

JTAG/HOST

XTAL1

SW_EN

VCO_VDD

VCO_GND

PLL_VDD

PLL_GND

EQ_VDD

EQ_GND

A_VDD

A_GND

BUFF_VDD

BUFF_GND

Buffer

SDI

XTAL2

XTAL_OUT

SMPTE 425M

1080p 50/60

4:2:2 10-bit

Level B Level A

NGEN

AGC+

AGC-

DOUT[19:0]

PCLK

LOCKED

GS2961A 3Gb/s, HD, SD SDI Receiver, with Integrated

Adaptive Cable Equalizer

Product Brief

55975 - A September 2010

3 of 4

Pin Out

GS2961A Pin Out

The following table shows the pin difference between the GS2960A and the GS2961A:

132 45678910

PCLK

DVB_ASI

20bit/

10bit

SDO

STANDBY

RSV

JTAG/

HOST

RESET

_TRST

A_VDD

CORE

_GND

SDO

VBG

SDI

BUFF_

VDD

SDO_

EN/DIS

LB_CONT

VCO_

VDD

VCO_

GND

RSV

PLL_

VDD

A_GND

STAT0 STAT1

STAT2

STAT3

STAT4 STAT5

CORE

_GND

CORE

_GND

CORE

_GND

CORE

_VDD

CORE

_VDD

CORE

_VDD

CORE

_VDD

DOUT1

DOUT0 DOUT2 DOUT3

DOUT4 DOUT5

DOUT6 DOUT7

DOUT8 DOUT9

DOUT10 DOUT11

DOUT14 DOUT13

DOUT16 DOUT15

DOUT18 DOUT17

DOUT19

DOUT12

IO_VDD

IO_GND

PLL_

VDD

PLL_

GND

PLL_

VDD

A_GND

RC_BYP

SW_EN IO_GND IO_VDD

EQ_VDD EQ_GND

PLL_

GND

PLL_

GND

AGC+ RSV

SDOUT_

TDO

CS_

TMS

SDIN_

TDI

SCLK_

TCK

SMPTE_

BYPASS

IO_GND

IO_VDD

TIM_861

XTAL_

OUT

XTAL2

XTAL1

IO_GND

IO_VDD

IOPROC_

EN/DIS

AGC- A_GND

BUFF_

GND

CORE

_GND

RSV

CORE

_GND

Pin Number GS2960A GS2961A Functional Description of the GS2961A Pins

E1 SDI_VDD EQ_VDD POWER pin for the EQ.

E2 SDI_GND EQ_GND GND pin for the EQ.

F1 TERM AGC+ Attach the AGC capacitor between this pin and AGC-.

G1RSVAGC- Attach the AGC capacitor between this pin and AGC+.

G2RSVA_GND Level adjust for the Equalizer.

G4RSV CORE_GND GND connection – digital logic.

H3 RSV CORE_GND GND connection – digital logic.

P1-P3 P4-P4

GS2961AIBE3

Mfr. #:

Buy GS2961AIBE3

Manufacturer:

Semtech

Description:

IC RECEIVER CBL EQUALIZER 100BGA

Lifecycle:

New from this manufacturer.

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GS2961AIBE3