9397 750 15193 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 4 July 2005 10 of 18
Philips Semiconductors
74ALVT16374
16-bit edge-triggered D-type flip-flop; 3-state
11. Dynamic characteristics
[1] Typical values are at V
CC
= 2.5 V and T
amb
= 25 °C.
[2] Typical values are at V
CC
= 3.3 V and T
amb
= 25 °C.
Table 8: Dynamic characteristics
T
amb
=
40
°
C to +85
°
C; GND = 0 V; for test circuit see Figure 9.
Symbol Parameter Conditions Min Typ Max Unit
V
CC
= 2.5 V ± 0.2 V
[1]
f
max
maximum clock frequency see Figure 5 150 - - MHz
t
PLH
propagation delay nCP to nQx see Figure 5 1.5 2.6 4.2 ns
t
PHL
propagation delay nCP to nQx see Figure 5 1.5 2.8 4.5 ns
t
PZH
output enable time to HIGH-level see Figure 6 1.0 3.4 5.6 ns
t
PZL
output enable time to LOW-level see Figure 7 1.0 2.6 4.7 ns
t
PHZ
output disable time from HIGH-level see Figure 6 2.0 2.7 4.4 ns
t
PLZ
output disable time from LOW-level see Figure 7 1.0 2.0 3.3 ns
t
su(H)
setup time HIGH nDx to nCP see Figure 8 1.0 0 - ns
t
su(L)
setup time LOW nDx to nCP see Figure 8 1.5 0.4 - ns
t
h(H)
hold time HIGH nDx to nCP see Figure 8 0.5 0 - ns
t
h(L)
hold time LOW nDx to nCP see Figure 8 0.5 0 - ns
t
WH
nCP pulse width HIGH see Figure 5 1.5 - - ns
t
WL
nCP pulse width LOW see Figure 5 1.5 - - ns
V
CC
= 3.3 V ± 0.3 V
[2]
f
max
maximum clock frequency see Figure 5 250 - - MHz
t
PLH
propagation delay nCP to nQx see Figure 5 1.0 2.1 3.2 ns
t
PHL
propagation delay nCP to nQx see Figure 5 1.0 2.3 3.2 ns
t
PZH
output enable time to HIGH-level see Figure 6 1.0 2.3 3.8 ns
t
PZL
output enable time to LOW-level see Figure 7 1.0 2.0 3.2 ns
t
PHZ
output disable time from HIGH-level see Figure 6 1.0 2.7 4.2 ns
t
PLZ
output disable time from LOW-level see Figure 7 1.0 2.6 3.6 ns
t
su(H)
setup time HIGH nDx to nCP see Figure 8 1.0 0 - ns
t
su(L)
setup time LOW nDx to nCP see Figure 8 1.5 0 - ns
t
h(H)
hold time HIGH nDx to nCP see Figure 8 0.5 0 - ns
t
h(L)
hold time LOW nDx to nCP see Figure 8 0.5 0 - ns
t
WH
nCP pulse width HIGH see Figure 5 1.5 - - ns
t
WL
nCP pulse width LOW see Figure 5 1.5 - - ns
9397 750 15193 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 4 July 2005 11 of 18
Philips Semiconductors
74ALVT16374
16-bit edge-triggered D-type flip-flop; 3-state
12. Waveforms
Measurement points are given in Table 9.
V
OL
and V
OH
are typical voltage output drop that occur with the output load.
Fig 5. Propagation delay clock input to output, clock pulse width and maximum clock
frequency
Measurement points are given in Table 9.
V
OH
is typical voltage output drop that occur with the output load.
Fig 6. 3-state output enable time to HIGH-level and output disable time from HIGH-level
Measurement points are given in Table 9.
V
OL
is typical voltage output drop that occur with the output load.
Fig 7. 3-state output enable time to LOW-level and output disable time from LOW-level
001aad250
V
M
V
M
V
M
V
M
V
M
t
PLH
t
PHL
t
WL
t
WH
input nCP
output nQx
1/f
max
V
OH
V
I
V
OL
0 V
001aad251
input nOE
output nQx
V
M
V
Y
V
M
t
PHZ
t
PZH
V
M
V
OH
V
I
0 V
0 V
001aad253
input nOE
output nQx
V
M
V
X
V
M
t
PLZ
t
PZL
V
M
V
OL
V
OH
V
I
0 V
9397 750 15193 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 4 July 2005 12 of 18
Philips Semiconductors
74ALVT16374
16-bit edge-triggered D-type flip-flop; 3-state
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Fig 8. Data setup and hold times
Table 9: Measurement points
Supply voltage Input Output
V
M
V
M
V
X
V
Y
3 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
0.3 V
2.7 V 0.5 × V
CC
0.5 × V
CC
V
OL
+ 0.15 V V
OH
0.15 V
001aad252
V
M
input nDx
output nCP
V
M
V
M
V
M
V
M
V
M
t
s(H)
t
h(H)
t
s(L)
t
h(L)
V
I
V
I
0 V
0 V

74ALVT16374DL,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Flip Flops 2.5/3.3V 16-BIT
Lifecycle:
New from this manufacturer.
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