7 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback April 25, 2014
IRFB4410ZPbF/IRFS4410ZPbF/IRFSL4410ZPbF
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple ≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P. W .
Period
* V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
1K
VCC
DUT
0
L
20K
Vds
Vgs
Id
Vgs(th)
Qgs1
Qgs2QgdQgodr
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
V
DS
+
-
V
DD
DRIVER
15V
20V
t
p
V
(BR)DSS
I
AS
V
GS
V
DD
V
DS
L
D
D.U.T
+
-
Second Pulse Width < 1μs
Duty Factor < 0.1%
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
