Technical information DVIULC6-4SC6
6/12 Doc ID 11599 Rev 4
3 Technical information
3.1 Surge protection
The DVIULC6-4SC6 is particularly optimized to perform ESD surge protection based on the
rail to rail topology.
The clamping voltage V
CL
can be calculated as follows:
V
CL
+ = V
BUS
+ V
F,
for positive surges
V
CL
- = - V
F,
for negative surges
with: V
F
= V
T
+ R
d
.I
p
V
F
= forward drop voltage, V
T
= forward drop threshold voltage)
Calculation example
We can assume that the value of the dynamic resistance of the clamping diode is typically:
R
d
= 1.4 and V
T
= 1.2 V.
For an IEC 61000-4-2 surge Level 4 (Contact Discharge: V
g
= 8 kV, R
g
= 330 ),
V
BUS
= +5 V, and, in a first approximation, we assume that: I
p
= V
g
/ R
g
= 24 A.
We find:
V
CL
+ = +39 V
V
CL
- = -34 V
Note: The calculations do not take into account phenomena due to parasitic inductances.
3.2 Surge protection application example
If we consider that the connections from the pin V
BUS
to V
CC
and from GND to PCB GND
plane are two tracks 10 mm long and 0.5 mm wide, we can assume that the parasitic
inductances, L
W
of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs,
due to the rise time of this spike (tr = 1 ns), the voltage V
CL
has an extra value equal to
L
W
·dI/dt.
The dI/dt is calculated as: dI/dt = I
p
/t
r
= 24 A/ns for an IEC 61000-4-2 surge level 4 (contact
discharge V
g
= 8 kV, R
g
= 330
The over voltage due to the parasitic inductances is: L
W
.dI/dt = 6 x 24 = 144 V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be:
V
CL
+ = +39 + 144 = 183 V
V
CL
- = -34 - 144 = -178 V
We can reduce as much as possible these phenomena with simple layout optimization.
This is the reason why some recommendations have to be followed (see Section 3.3: How
to ensure good ESD protection).
