MAX1174BCUP+T Datasheet MAX1174BCUP+, MAX1174BCUP+T | P7-P9

Detailed Description

Converter Operation

The MAX1156/MAX1158/MAX1174 use a successive-

approximation (SAR) conversion technique with an

inherent track-and-hold (T/H) stage to convert an ana-

log input into a 14-bit digital output. Parallel outputs

provide a high-speed interface to microprocessors

(µPs). The Functional Diagram shows a simplified inter-

nal architecture of the MAX1156/MAX1158/MAX1174.

Figure 3 shows a typical application circuit for the

MAX1156/MAX1158/MAX1174.

Analog Input

Input Scaler

The MAX1156/MAX1158/MAX1174 have an input

scaler, which allows conversion of true bipolar input

voltages and input voltages greater than the power

supply, while operating from a single +5V analog sup-

ply. The input scaler attenuates and shifts the analog

input to match the input range of the internal DAC. The

MAX1156 has a unipolar input voltage range of 0 to

+10V. The MAX1158 input voltage range is ±10V while

the MAX1174 input voltage range is ±5V. Figure 4

shows the equivalent input circuit of the MAX1156/

MAX1158/MAX1174. This circuit limits the current going

into or out of AIN to less than 1.8mA.

Track and Hold (T/H)

In track mode, the internal hold capacitor acquires the

analog signal (see Figure 4). In hold mode, the T/H

switches open and the capacitive DAC samples the

analog input. During the acquisition, the analog input

(AIN) charges capacitor C

HOLD

. The acquisition ends

on the second falling edge of CS. At this instant, the

T/H switches open. The retained charge on C

HOLD

rep-

resents a sample of the input. In hold mode, the capac-

itive DAC adjusts during the remainder of the

conversion time to restore node T/H OUT to zero within

the limits of 14-bit resolution. Force CS low to put valid

data on the bus after conversion is complete.

MAX1156/MAX1158/MAX1174

14-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

_______________________________________________________________________________________ 7

Pin Description (continued)

PIN NAME FUNCTION

13 HBEN

High-Byte Enable Input. Used to multiplex the 14-bit conversion result.

1: Most significant byte available on the data bus.

0: Least significant byte available on the data bus.

14 CS

Convert Start. The first falling edge of CS powers up the device and enables acquire mode when R/C

is low. The second falling edge of CS starts conversion. The third falling edge of CS loads the result

onto the bus when R/C is high.

15 DGND Digital Ground

16 DV

Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.

17 D0/D8 Three-State Digital Data Output. D0 is the LSB.

18 D1/D9 Three-State Digital Data Output

19 D2/D10 Three-State Digital Data Output

20 D3/D11 Three-State Digital Data Output

DGND

1mA

LOAD

= 20pF

DO–D13

LOAD

= 20pF

1mA

DGND

a) HIGH-Z TO V

TO V

, AND

TO HIGH-Z

b) HIGH-Z TO V

TO V

, AND

TO HIGH-Z

Figure 1. Load Circuits

MAX1156/MAX1158/MAX1174

Power-Down Modes

Select standby mode or shutdown mode with the R/C

bit during the second falling edge of CS (see the

Selecting Standby or Shutdown Mode section). The

MAX1156/MAX1158/MAX1174 automatically enter

either standby mode (reference and buffer on) or shut-

down (reference and buffer off) after each conversion,

depending on the status of R/C during the second

falling edge of CS.

Internal Clock

The MAX1156/MAX1158/MAX1174 generate an internal

conversion clock to free the microprocessor from the

burden of running the SAR conversion clock. Total con-

version time (t

CONV

) after entering hold mode (second

falling edge of CS) to end of conversion (EOC) falling is

4.7µs (max).

Applications Information

Starting a Conversion

CS and R/C control acquisition and conversion in the

MAX1156/MAX1158/MAX1174 (see Figure 2). The first

falling edge of CS powers up the device and puts it in

acquire mode if R/C is low. The convert start is ignored

if R/C is high. The MAX1156/MAX1158/MAX1174 need

at least 12ms (C

REFADJ

= 0.1µF, C

REF

= 10µF) for the

internal reference to wake up and settle before starting

the conversion, if powering up from shutdown.

14-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

8 _______________________________________________________________________________________

R/C

REF POWER-

DOWN CONTROL

EOC

ACQ

CONV

CSH

CSL

EOC

HBEN

D7/D15–D0/D8

HIGH/LOW

BYTE VALID

HIGH/LOW

BYTE VALID

DO1

HIGH-Z

Figure 2. MAX1156/MAX1158/MAX1174 Timing Diagram

D0–D7

D8–D13

µP DATA

BUS

AGND DGND

+5V ANALOG +5V DIGITAL

ANALOG INPUT AIN

HBEN

EOC

R/C

REF

REFADJ

HIGH

BYTE

LOW

BYTE

10µF

0.1µF

0.1µF 0.1µF

MAX1156

MAX1158

MAX1174

Figure 3. Typical Application Circuit for the MAX1156/MAX1158/

MAX1174

Selecting Standby or Shutdown Mode

The MAX1156/MAX1158/MAX1174 have a selectable

standby or low-power shutdown mode. In standby

mode, the ADC’s internal reference and reference

buffer do not power down between conversions, elimi-

nating the need to wait for the reference to power up

before performing the next conversion. Shutdown mode

powers down the reference and reference buffer after

completing a conversion. The reference and reference

buffer require a minimum of 12ms (C

REFADJ

= 0.1µF,

REF

= 10µF) to power up and settle from shutdown.

The state of R/C at the second falling edge of CS

selects which power-down mode the MAX1156/

MAX1158/MAX1174 enter upon conversion completion.

Holding R/C low causes the MAX1156/MAX1158/

MAX1174 to enter standby mode. The reference and

buffer are left on after the conversion completes. R/C

high causes the MAX1156/MAX1158/MAX1174 to enter

shutdown mode and power down the reference and

buffer after conversion (see Figures 5 and 6). Set the

voltage at R/C high during the second falling edge of

CS to realize the lowest current operation.

Standby Mode

While in standby mode, the supply current is less than

3.7mA (typ). The next falling edge of CS with R/C low

causes the MAX1156/MAX1158/MAX1174 to exit stand-

by mode and begin acquisition. The reference and ref-

erence buffer remain active to allow quick turn-on time.

Shutdown Mode

In shutdown mode, the reference and reference buffer

are shut down between conversions. Shutdown mode

reduces supply current to 0.5µA (typ) immediately after

the conversion. The next falling edge of CS with R/C

low causes the reference and buffer to wake up and

enter acquisition mode. To achieve 14-bit accuracy,

allow 12ms (C

REFADJ

= 0.1µF, C

REF

= 10µF) for the

internal reference to wake up.

Internal and External Reference

Internal Reference

The internal reference of the MAX1156/MAX1158/

MAX1174 is internally buffered to provide +4.096V out-

put at REF. Bypass REF to AGND and REFADJ to

AGND with 10µF and 0.1µF, respectively. Sink or

source current at REFADJ to make fine adjustments to

the internal reference. The input impedance of REFADJ

is nominally 5kΩ. Use the circuit of Figure 7 to adjust

the internal reference to ±1.5%.

MAX1156/MAX1158/MAX1174

14-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

_______________________________________________________________________________________ 9

S1, S2 = T/H SWITCH

S3 = POWER-DOWN

(MAX1158/MAX1174 ONLY)

AIN

3.4kΩ

REF

T/H OUT

HOLD

TRACK

R2 = 7.85kΩ (MAX1158)

OR 3.92kΩ (MAX1156/MAX1174)

R3 = 5.45kΩ (MAX1158)

OR 17.79kΩ (MAX1156/MAX1174)

HOLD

30pF

POWER-

DOWN

161Ω

MAX1158/MAX1174

AIN

3.4kΩ

T/H OUT

HOLD

TRACK

HOLD

30pF

161Ω

MAX1156

Figure 4. Equivalent Input Circuit

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

MAX1174BCUP+T

Mfr. #:

Buy MAX1174BCUP+T

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 14-Bit 135ksps 4.2V Precision ADC

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MAX1174BCUP+T

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