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MPC9351AC

P1-P3P4-P6P7-P9P10-P12P13-P14
REVISION 7 3/14/16 7 ©2016 INTEGRATED DEVICE TECHNOLOGY, INC.
MPC9351 DATA SHEET
APPLICATIONS INFORMATION
Programming the MPC9351
The MPC9351 clock driver outputs can be configured into
several divider modes; in addition, the external feedback of
the device allows for flexibility in establishing various input to
output frequency relationships. The output divider of the four
output groups allows the user to configure the outputs into
1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensures that the output duty cycle is always 50%.
Table 9 illustrates the various output configurations. The
table describes the outputs using the input clock frequency
CLK as a reference.
The output division settings establish the output
relationship. In addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 25MHz to
200MHz, while the VCO frequency range is specified from
200MHz to 400MHz and should not be exceeded for stable
operation.
Using the MPC9351 in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC9351. For these applications, the MPC9351 offers a
differential LVPECL clock input pair as a PLL reference. This
allows for the use of differential LVPECL primary clock
distribution devices such as the Freescale MC100EP111 or
MC10EP222, taking advantage of its superior low-skew
performance. Clock trees using LVPECL for clock
distribution, and the MPC9351 as LVCMOS PLL fanout buffer
with zero insertion delay, will show significantly lower clock
skew than clock distributions developed from CMOS fanout
buffers.
The external feedback option of the MPC9351 PLL allows
for its use as a zero-delay buffer. The PLL aligns the feedback
clock output edge with the clock input reference edge and
virtually eliminates the propagation delay through the device.
The remaining insertion delay (skew error) of the
MPC9351 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset (SPO or t
()
), I/O jitter
(t
JIT()
, phase or long-term jitter), feedback path delay and
the output-to-output skew (t
SK(O)
relative to the feedback
output.
Figure 3. MPC9351 Zero-Delay Configuration
(Feedback of QD4)
Table 9. Output Frequency Relationship
(1)
for an Example Configuration
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB. More frequency ratios are
available by the connection of QA to the feedback input (EXT_FB).
Inputs Outputs
FSELA FSELB FSELC FSELD QA QB QC QD
0 0 0 0 2 * CLK CLK CLK CLK
0 0 0 1 2 * CLK CLK CLK CLK 2
0 0 1 0 4 * CLK 2 * CLK CLK 2* CLK
0 0 1 1 4 * CLK 2 * CLK CLK CLK
0 1 0 0 2 * CLK CLK 2 CLK CLK
0 1 0 1 2 * CLK CLK 2 CLK CLK 2
0 1 1 0 4 * CLK CLK CLK 2 * CLK
0 1 1 1 4 * CLK CLK CLK CLK
1 0 0 0 CLK CLK CLK CLK
1 0 0 1 CLK CLK CLK CLK 2
1 0 1 0 2 * CLK 2 * CLK CLK 2 * CLK
1 0 1 1 2 * CLK 2 * CLK CLK CLK
1 1 0 0 CLK CLK 2 CLK CLK
1 1 0 1 CLK CLK 2 CLK CLK 2
1 1 1 0 2 * CLK CLK CLK 2 * CLK
1 1 1 1 2 * CLK CLK CLK CLK
MPC9351
TCLK
QA
fref = 100 MHz
REF_SEL
PLL_EN
FSELA
FSELB
FSELC
FSELD
Ext_FB
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
2 x 100 MHz
2 x 100 MHz
4 x 100 MHz
100 MHz (Feedback)
1
1
1
0
0
0
LOW VOLTAGE PLL CLOCK DRIVER 8 REVISION 7 3/14/16
MPC9351 DATA SHEET
Calculation of Part-to-Part Skew
The MPC9351 zero-delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC9351 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
t
SK(PP)
= t
()
+ t
SK(O)
+ t
PD, LINE(FB)
+ t
JIT()
· CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Figure 4. MPC9351 Maximum Device-to-Device Skew
Due to the statistical nature of I/O jitter, a RMS value (1 )
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 10.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation, an
I/O jitter confidence factor of 99.7% ( 3) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –251 ps to 351 ps relative to TCLK (V
CC
= 3.3 V and
f
VCO
= 400 MHz):
t
SK(PP)
=[–50 ps...150 ps] + [–150 ps...150 ps] +
[(17ps · –3)...(17ps ·3)] + t
PD, LINE(FB)
t
SK(PP)
=[–251 ps...351 ps] + t
PD, LINE(FB)
Above equation uses the maximum I/O jitter number
shown in the AC characteristic table for V
CC
= 3.3 V (17 ps
RMS). I/O jitter is frequency dependant with a maximum at
the lowest VCO frequency (200 MHz for the MPC9351).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
characteristics in Figure 5 and Figure 6 can be used to derive
a smaller I/O jitter number at the specific VCO frequency,
resulting in tighter timing limits in zero-delay mode and for
part-to-part skew (t
SK(PP)
).
Figure 5. Maximum I/O Jitter (RMS)
versus Frequency for V
CC
= 2.5 V
Figure 6. Maximum I/O Jitter (RMS)
versus Frequency for V
CC
= 3.3 V
Power Supply Filtering
The MPC9351 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Noise on the
V
CCA
(PLL) power supply impacts the device characteristics,
for instance, I/O jitter. The MPC9351 provides separate
power supplies for the output buffers (V
CC
) and the
phase-locked loop (V
CCA
) of the device. The purpose of this
design technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment, where it
is more difficult to minimize noise on the power supplies, a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the V
CCA
pin for the MPC9351. Figure 7 illustrates a typical power
supply filter scheme. The MPC9351 frequency and phase
stability is most susceptible to noise with spectral content in
Table 10. Confidence Factor CF
CF Probability of Clock Edge within the Distribution
1 0.68268948
2 0.95449988
3 0.99730007
4 0.99993663
5 0.99999943
6 0.99999999
t
PD,LINE(FB)
t
JIT()
+t
SK(O)
—t(ý)
+t
()
t
JIT()
+t
SK(O)
t
SK(PP)
Max. skew
TCLK
Common
QFB
Device 1
Any Q
Device 1
QFB
Device2
Any Q
Device 2
30
25
20
15
10
5
0
75 225 250 275 300 325
VCO Frequency [MHz]
t
JIT(ý)
[ps] ms
Max. I/O Jitter versus Frequency
350 375 400
30
25
20
15
10
5
0
75 225 250 275 300 325
VCO Frequency [MHz]
t
JIT(ý)
[ps] ms
Max. I/O Jitter versus Frequency
350 375 400
REVISION 7 3/14/16 9 ©2016 INTEGRATED DEVICE TECHNOLOGY, INC.
MPC9351 DATA SHEET
the 100 kHz to 20MHz range; therefore, the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
across the series filter resistor (R
F
). From the data sheet, the
I
CCA
current (the current sourced through the V
CCA
pin) is
typically 3mA (5mA maximum), assuming that a minimum of
2.325V (V
CC
=3.3V or V
CC
= 2.5V) must be maintained on
the V
CCA
pin. The resistor R
F
shown in Figure 7 must have a
resistance of 270 (V
CC
= 3.3 V) or 9–10 (V
CC
= 2.5 V) to
meet the voltage drop criteria.
Figure 7. V
CCA
Power Supply Filter
The minimum values for R
F
and the filter capacitor C
F
are
defined by the required filter characteristics. The RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7, the filter cut-off frequency is around
3–5 kHz, and the noise attenuation at 100 kHz is better than
42dB.
As the noise frequency crosses the series resonant point
of an individual capacitor, its overall impedance begins to
look inductive, and thus, increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9351 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Driving Transmission Lines
The MPC9351 clock driver was designed to drive high-
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 resistance to V
CC
2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9351 clock driver. For the series terminated
case, however, there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 8 illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9351 clock driver is effectively doubled
due to its capability to drive multiple lines.
Figure 8. Single versus Dual Transmission Lines
The waveform plots in Figure 9 show the simulation
results of an output driving a single line versus two lines. In
both cases, the drive capability of the MPC9351 output buffer
is more than sufficient to drive 50 transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43ps exists between the two
differently loaded outputs. This suggests that dual line driving
need not be used exclusively to maintain the tight
output-to-output skew of the MPC9351. The output waveform
in Figure 9 shows a step in the waveform. This step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36 series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
V
L
=V
S
(Z
0
(R
S
+ R
0
+ Z
0
))
Z
0
=50 || 50
R
S
=36 || 36
R
0
=14
V
L
= 3.0 (25 (18 + 17 + 25)
=1.31 V
At the load end, the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
V
CCA
V
CC
MPC9351
10 nF
R
F
= 270 for V
CC
= 3.3 V
R
F
= 9–10 for V
CC
= 2.5 V
C
F
33...100 nF
R
F
V
CC
C
F
= 1 F for V
CC
= 3.3 V
C
F
= 22 F for V
CC
= 2.5 V
14
IN
MPC9351
Output
Buffer
R
S
= 36
Z
O
= 50
OutA
14
IN
MPC9351
Output
Buffer
R
S
= 36
Z
O
= 50
OutB0
R
S
= 36
Z
O
= 50
OutB1
P1-P3P4-P6P7-P9P10-P12P13-P14

MPC9351AC

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Manufacturer:
IDT
Description:
Clock Drivers & Distribution FSL1-9 LVCMOS/LVPECL LVCMOS PLL Clk Gen
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