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NCP5214MNR2

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NCP5214
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22
ADAPTIVE
RAMP
OSC
VDDQ
PWM
LOGIC
A
PWM
COMP
VIN
PGND
VREF
TGDDQ
SWDDQ
BGDDQ
PGND
COMP
FBDDQ
VDDQ
L
C2
C1
R3
C3
R4
R2
R1
COUT
VIN
Q2
Q1
CIN
ERROR
AMP
VBOOST
NCP5214
ESR
OUTPUT
FILTER
COMPENSATION
NETWORK
MODULATOR
VCCP
VRAMP
Figure 39. Voltage Mode Buck Converter with Modulator, LC filter and Type III Compensation
Modulator DC Gain can be calculated by:
G
MOD(DC)
+ 20 log
V
IN
V
RAMP
(eq. 20)
LC filter double pole and ESR zero break frequencies are
defined by:
f
PLC
+
1
2p L C
OUT
Ǹ
(eq. 21)
f
ZESR
+
1
2p ESR C
OUT
(eq. 22)
Compensation network DC Gain can be calculated by the
equation:
G
COMP(DC)
+ 20 log
R
3
R
1
(eq. 23)
Type III compensation poles and zeros break frequencies
are defined by the below equations:
f
Z1
+
1
2p R
3
C
2
(eq. 24)
f
P1
+
1
2p R
3
ǒ
C
1
C
2
C
1
)C
2
Ǔ
(eq. 25)
f
Z2
+
1
2p (R
1
) R
4
) C
3
(eq. 26)
f
P2
+
1
2p R
4
C
3
(eq. 27)
80
100
Open Loop Error
Amp Gain
Compensation
Gain
Closed Loop Gain
60
40
20
0
−20
−40
−60
GAIN (dB)
10 100 1 k 10 k 100 k 1 M 10 M
f
Z1
f
Z2
f
P1
f
P2
f
ZESR
f
PLC
Modulator & Filter Gain
20 log
20 log
R
3
R
1
V
IN
V
RAMP
FREQUENCY (Hz)
Figure 40. Asymptotic Bode Plot of the Converter Gain
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23
Close loop system bandwidth can be calculated by:
BW +
R
3
R
1
V
IN
V
RAMP
1
2p L C
OUT
Ǹ
(eq. 28)
Since the ramp amplitude of the PWM modulator has a
voltage feedforward function, the ramp amplitude is a
function of V
IN
which can be determined by:
V
RAMP
+ 1.25 V ) 0.045 (V
IN
−5.0 V)
(eq. 29)
Below are some guidelines for setting the compensation
components:
1. Set a value for R
1
between 2.0 kW and 5.0 kW.
2. Set a target for the close loop bandwidth which
should be less than 50% of the switching
frequency.
3. Pick compensation DC gain (R
3
/R
1
) for desired
close loop bandwidth.
4. Place 1st zero at half filter double pole.
5. Place 1st pole at ESR zero.
6. Place 2nd zero at filter double pole.
7. Place 2nd pole at half the switching frequency.
By using the above equations and guidelines, the
compensation components values can be determined by the
equations below:
R
3
+
2p BW V
RAMP
R
1
L C
OUT
Ǹ
V
IN
(eq. 30)
C
2
+
2 L C
OUT
Ǹ
R
3
(eq. 31)
C
1
+
C
2
ǒ
R
3
C
2
ESR C
OUT
Ǔ
* 1
(eq. 32)
R
4
+
R
1
p f
SW
L C
OUT
Ǹ
* 1
(eq. 33)
C
3
+
1
p R
4
f
SW
(eq. 34)
The modulator and filter gain, compensation gain, and
close loop gain asymptotic Bode plot can be drawn by the
calculated results to check the compensation gain and close
loop gain obtained. An example of asymptotic Bode plot is
shown in Figure 40.
The phase of the output filter can be calculated by:
Phase
(Filter)
+ −tan
−1
(2pf ESR C
OUT
)−tan
−1
ǒ
2pf ESR ) DCR C
OUT
2pf
2
L C
OUT
−1
Ǔ
(eq. 35)
where the DCR of the inductor can be neglected if the DCR is small.
The phase of the Type III compensation network can be calculated by:
Phase
(TypeIII)
+ −90° ) tan
−1
(2pf R
3
C
2
)−tan
−1
ǒ
2pf R
3
C
1
C
2
C
1
) C
2
Ǔ
(eq. 36)
) tan
−1
(2pf (R
1
) R
4
) C
3
)−tan
−1
(2pf R
4
C
3
)
The close loop phase can be calculated by summing the
filter phase and compensation phase:
Phase
(CloseLoop)
+ Phase
(Filter)
) Phase
(TypeIII)
(eq. 37)
Then the close loop phase margin can be estimated by:
Phase
(Margin)
+ Phase
(CloseLoop)
* (*180°)
(eq. 38)
It should be checked that closed loop gain has a 0 dB gain
crossing with −20 dB/decade slope and a phase margin of
45° or greater. The compensation components values may
require some adjustment to meet these requirements.
Besides, the compensation gain should be checked with the
error amplifier open loop gain to make sure that it is
bounded by the error amplifier open loop gain.
The poles and zeros locations and hence the
compensation network components values may need to be
further fine tuned after actual system testing and analysis.
Feedback Resistor Divider
The output voltage of the buck regulator can be adjusted
by the feedback resistor divider formed by R
1
and R
2
. Once
the value of R
1
is selected when determining the
compensation components, the value of R
2
can be obtained
by:
R
2
+
0.8 R
1
V
OUT
−0.8
(eq. 39)
It is recommended to adjust the value of R
2
to fine−tune
the output voltage when it is necessary. The value of R
1
should not be changed since the compensation DC gain and
the 2
nd
zero break frequency of the compensation gain are
contributed by R
1
. If the value of R
1
is changed, the
compensation, the close loop bandwidth and phase margin,
and the system stability will be affected. Besides, it is
recommended to use resistors with at least 1% tolerance for
R
1
and R
2
.
Soft−Start of Buck Regulator
A VDDQ soft−start feature is incorporated in the device
to prevent surge current from power supply and output
voltage overshoot during power up. When VDDQEN,
VCCA, and VOCDDQ rise above their respective upper
threshold voltages, the external soft−start capacitor C
SS
will be charged up by a constant current source, I
ss
. When
the soft−start voltage (Vcss) rises above the SS_EN voltage
(X50 mV), the BGDDQ and TGDDQ will start switching
and VDDQ output will ramp up with VFBDDQ following
the soft−start voltage. When the soft−start voltage reaches
the SS_OK voltage (XVref + 50 mV), the soft−start of
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24
VDDQ is finished. The C
ss
will continue to charge up until
it reaches about 2.5 V to 3.0 V.
The soft−start time t
ss
can be programmed by the
soft−start capacitor according to the following equation:
t
ss
[
0.8 C
ss
I
ss
(eq. 40)
Ceramic capacitors with low tolerance and low
temperature coefficient, such as B, X5R, X7R ceramic
capacitors are recommended to be used as the C
SS
. Ceramic
capacitors with Y5V temperature characteristic are not
recommended.
Soft−Start of VTT Active Terminator
The VTT source current limit is used as a constant
current source to charge up the VTT output capacitor
during VTT soft−start. Besides, the VTT source current
limit is reduced to about 1.0 A for 128 internal clock cycles
to minimize the inrush current during VTT soft−start.
Therefore, the VTT soft−start time t
SSVTT
can be estimated
by the equation:
t
SSVTT
[
C
OUTVTT
VTT
I
LIMVTSS
(eq. 41)
where C
OUTVTT
is the capacitance of VTT output capacitor
and I
LIMVTSS
is the VTT soft−start source current limit.
Boost Supply Diode and Capacitor
An external diode and capacitor are used to generate the
boost voltage for the supply of the high−side gate driver of
the bulk regulator. Schottky diode with low forward
voltage should be used to ensure higher floating gate drive
voltage can be applied across the gate and the source of the
high−side MOSFET. A Schottky diode with 30 V reverse
voltage and 0.5 A DC current ratings can be used as the
boost supply diode for most applications. A 0.1 mF to
0.22 mF ceramic capacitor should be sufficient as the boost
capacitor.
VTTI Input Power Supply for VTT and VTTR
Both VTT and VTTR are supplied by VTTI for sourcing
current. VTTI is normally connected to the VDDQ output
for optimum performance. If VTTI is connected to VDDQ,
no bypass capacitor is required to add to VTTI since the
bulk capacitor at VDDQ output is sufficiently large.
Besides, the maximum load current of VDDQ is the sum of
I
VDDQ(max)
and I
VTT(max)
when making electrical design
and components selection of the VDDQ buck regulator.
VTTI can also be connected to an external voltage source.
However, extra power dissipation will be generated from
the internal VTT high−side MOSFET and more
heatsinking is required if the external voltage is higher than
VDDQ. Whereas, the headroom will be limit by the R
DS(on)
of the VTT linear regulator high−side MOSFET, and the
maximum VTT output current with VTT within regulation
window will also be reduced if the external voltage is lower
than VDDQ. Besides, the VTTI pin input must be bypassed
to VTTGND with at least a 10 mF capacitor if external
voltage source is used.
Design Example
A design example of a VDDQ bulk converter with the
following design parameters is shown below:
DDR2 VDDQ bulk converter design parameters:
1. Input voltage range: 7.0 V to 20 V.
2. Nominal V
OUT
: 1.8 V.
3. Static tolerance: 2% ("36 mV).
4. Transient tolerance: "100 mV.
5. Maximum output current: 10 A
(I
VDDQ(max)
= 8.0 A, I
VTT(max)
= 2.0 A).
6. Load transient step: 1.0 A to 8.0 A.
7. Switching frequency: 400 kHz.
8. Bandwidth: 100 kHz.
9. Soft−start time: 400 ms.
a. Calculate input capacitor rms ripple current rating and
voltage rating:
I
CIN(RMS)
w 10 A
1.836 V
8.0 V
*
ǒ
1.836 V
8.0 V
Ǔ
2
Ǹ
+ 4.2 A
(eq. 42)
V
CIN(rating)
w 20 1.25 V + 25 V
(eq. 43)
Therefore, two 10 mF 25 V ceramic capacitors with 1210
size in parallel are used.
b.Calculate inductance, rated current and DCR of
inductor:
First, suppose ripple current is 0.3 times the maximum
output current, such that:
L w
(20 V−1.836 V) 1.836 V
0.3 10 A 20 V 400 kHz
+ 1.39 mH
(eq. 44)
Second, the overshoot requirement at load release is then
considered and supposes two 220 mF capacitors in parallel
are used as an initially guess, such that:
L
v
440 mF
(
(100 mV )1.836 V)
2
−(1.836 V)
2
)
ǒ
7A)
0.3 7A
2
Ǔ
2
+2.56 m
H
(eq. 4
5)
Thus, inductors with standard inductance values of
1.5 mH, 1.8 mH and 2.2 mH can be used. As a trade−off
between smaller overshoot and better efficiency, the
average value of 1.8 mH inductor is selected.
Then, the maximum rated DC current is calculated by:
I
L(rated)
+ 1.2
ǒ
10 A )
(20 V−1.836 V) 1.836 V
2 1.8 mH 400 kHz 20
Ǔ
(eq. 4
6)
+ 13.39 A
Therefore, inductor with maximum rated DC current of
14 A or larger can be used.
Finally, the DCR of inductor is 2.0 mW per mH of
inductance as a rule of thumb, then:
DCR +
2mW
1 mH
1.8 mH + 3.6 mW
(eq. 47)
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NCP5214MNR2

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IC REG CTRLR DDR 2OUT 22DFN
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