Philips Semiconductors Product data sheet
PCA9564Parallel bus to I
2
C-bus controller
2006 Sep 01
24
AC CHARACTERISTICS (3.3 VOLT)
1,
2,
3
V
CC
= 3.3 V ± 0.3 V, T
amb
= –40 °C to +85 °C, unless otherwise specified. (See page 25 for 2.5 V.)
LIMITS
SYMBOL PARAMETER
Min Max
UNIT
Reset Timing (See Figure 19)
t
WRES
Reset pulse width 10 — ns
t
RES
4,5
Time to reset 250 — ns
t
REC
Reset recovery time 0 — ns
Bus Timing (See Figure 20, 21)
t
AS
A0–A1 setup time to RD, WR LOW 0 — ns
t
AH
A0–A1 hold time from RD, WR LOW 7 — ns
t
CS
CE setup time to RD, WR LOW 0 — ns
t
CH
CE Hold time from RD, WR LOW 0 — ns
t
RW
WR, RD pulse width (Low time) 7 — ns
t
DD
Data valid after RD and CE LOW — 17 ns
t
DF
Data bus floating after RD or CE HIGH — 17 ns
t
DS
Data bus setup time before WR or CE HIGH (write cycle) 7 — ns
t
DH
Data hold time after WR HIGH 0 — ns
t
RWD
High time between read and/or write cycles 12 — ns
NOTES:
1. Parameters are valid over specified temperature and voltage range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of 5 ns
maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figures 20–21.
3. Test conditions for outputs: C
L
= 50 pF, R
L
= 500 Ω, except open drain outputs. Test conditions for open drain outputs: C
L
= 50 pF, R
L
= 1 kΩ
pullup to V
DD
.
4. Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.
5. Upon reset, the full delay will be the sum of t
RES
and the RC time constant of the SDA and SCL bus.
