Philips
Semiconductors
PCA9564
Parallel bus to I
2
C-bus controller
Product data sheet
Supersedes data of 2004 Jun 25
2006 Sep 01
INTEGRATED CIRCUITS
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I
2
C-bus controller
2
2006 Sep 01
FEATURES
Parallel-bus to I
2
C-bus protocol converter and interface
Both master and slave functions
Multi-master capability
Internal oscillator reduces external components
Operating supply voltage 2.3 V to 3.6 V
5 V tolerant I/Os
Standard and fast mode I
2
C capable and compatible with SMBus
ESD protection exceeds 2000 V HEM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which
exceed 100 mA.
Packages offered: DIP20, SO20, TSSOP20, HVQFN20
APPLICATIONS
Add I
2
C-bus port to controllers/processors that do not have one
Add additional I
2
C-bus ports to controllers/processors that need
multiple I
2
C-bus ports
Higher frequency, lower voltage migration path for the PCF8584
Converts 8 bits of parallel data to serial data stream to prevent
having to run a large number of traces across the entire PC board
DESCRIPTION
The PCA9564 is an integrated circuit designed in CMOS technology
that serves as an interface between most standard parallel-bus
microcontrollers/microprocessors and the serial I
2
C-bus and allows
the parallel bus system to communicate bi-directionally with the
I
2
C-bus. The PCA9564 can operate as a master or a slave and can
be a transmitter or receiver. Communication with the I
2
C-bus is
carried out on a byte-wise basis using interrupt or polled handshake.
The PCA9564 controls all the I
2
C-bus specific sequences, protocol,
arbitration and timing with no external timing element required.
The PCA9564 is similar to the PCF8584 but operates at lower
voltages and higher I@C frequencies. Other enhancements
requested by design engineers have also been incorporated.
Characteristic
PCA9564 PCF8584 Comments
Voltage range 2.3–3.6 V 4.5–5.5 V PCA9564 is 5 V
tolerant
Maximum
master mode
I
2
C frequency
360 kHz 90 kHz Faster I
2
C interface
Maximum slave
mode I
2
C
frequency
400 kHz 100 kHz Faster I
2
C interface
Clock source Internal External Less expensive and
more flexible with
internal oscillator
Parallel
interface
Fast
50 MHz
Slow Compatible with
faster processors
While the PCF8584 supported most parallel-bus microcontrollers/
microprocessors including the Intel 8049/8051, Motorola
6800/68000 and the Zilog Z80, the PCA9564 has been designed to
be very similar to the Philips standard 80C51 microcontroller I
2
C
hardware so the devices are not code compatible. Additionally, the
PCA9564 does not support the bus monitor “Snoop” mode nor the
long distance mode and is not footprint compatible with the
PCF8584.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER
20-Pin Plastic DIP –40 °C to +85 °C PCA9564N PCA9564N SOT146-1
20-Pin Plastic SO –40 °C to +85 °C PCA9564D PCA9564D SOT163-1
20-Pin Plastic TSSOP –40 °C to +85 °C PCA9564PW PCA9564 SOT360-1
20-Pin Plastic HVQFN –40 °C to +85 °C PCA9564BS 9564 SOT662-1
whole wafer –40 °C to +85 °C PCA9564U n/a n/a
Standard packing quantities and other packaging data are available at www.standardics.philips.com/packaging.
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I
2
C-bus controller
2006 Sep 01
3
PIN CONFIGURATION — DIP, SO, TSSOP
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20D0
D1
D2
D3
D4
D5
D6
D7
DNU
V
SS
V
DD
SDA
SCL
RESET
INT
A1
A0
RD
CE
WR10
SW02260
PIN CONFIGURATION — HVQFN
15
14
13
12
11
6
7
8
9
10
1
2
3
4
5
20
19
18
17
16
SW02261
TOP VIEW
D3
D4
D5
D6
D7
INT
RESET
A0
A1
SCL
D2
D1
D0
SDA
V
DD
DNU
RD
WR
CE
V
SS
PIN DESCRIPTION
PIN NUMBER
PIN
DIP, SO, TSSOP HVQFN
SYMBOL
PIN
TYPE
NAME AND FUNCTION
1, 2, 3, 4,
5, 6, 7, 8
1, 2, 3, 4, 5,
18, 19, 20
D0–D7 I/O Data Bus: Bi-directional 3-State data bus used to transfer commands, data and
status between the controller and the CPU. D0 is the least significant bit.
9 6 DNU Do not use: must be left floating (pulled LOW internally)
10 7
1
V
SS
Pwr Ground
11 8 WR I Write Strobe: When LOW and CE is also LOW, the contents of the data bus is
loaded into the addressed register. The transfer occurs on the rising edge of the
signal.
12 9 RD I Read Strobe: When LOW and CE is also LOW, causes the contents of the
addressed register to be presented on the data bus. The read cycle begins on the
falling edge of RD
.
13 10 CE I Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU
and the controller are enabled on D0–D7 as controlled by the WR
, RD and A0–A1
inputs. When HIGH, places the D0–D7 lines in the 3-State condition.
14, 15 11, 12 A0, A1 I Address Inputs: Selects the controller internal registers and ports for read/write
operations.
16 13 INT O Interrupt Request: Active-LOW, open-drain, output. This pin requires a pull-up
device.
17 14 RESET I Reset: A LOW level clears internal registers resets the I
2
C state machine.
18 15 SCL I/O I
2
C-bus serial clock input/output (open-drain).
19 16 SDA I/O I
2
C-bus serial data input/output (open-drain).
20 17 V
DD
Pwr Power Supply: 2.3 to 3.6 V
NOTES:
1. HVQFN package die supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must be connected to supply ground for
proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board
using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in
the PCB in the thermal pad region.

PCA9564D,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
I/O Controller Interface IC 400 KHZ I2C BUS CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
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