© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 10
1 Publication Order Number:
MC14094B/D
MC14094B
8-Stage Shift/Store Register
with Three-State Outputs
The MC14094B combines an 8−stage shift register with a data latch
for each stage and a 3−state output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The Q
S
output data is for use in
high−speed cascaded systems. The Q
S
output data is shifted on the
following negative clock transition for use in low−speed cascaded systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while
strobe is high.
Outputs of the eight data latches are controlled by 3−state buffers which
are placed in the high−impedance state by a logic Low on Output Enable.
Features
• 3−State Outputs
• Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature
Range
• Input Diode Protection
• Data Latch
• Dual Outputs for Data Out on Both Positive and
Negative Clock Transitions
• Useful for Serial−to−Parallel Data Conversion
• Pin−for−Pin Compatible with CD4094B
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage Range −0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V
DD
+ 0.5 V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±10 mA
P
D
Power Dissipation, per Package (Note 1) 500 mW
T
A
Ambient Temperature Range −55 to +125 °C
T
stg
Storage Temperature Range −65 to +150 °C
T
L
Lead Temperature
(8−Second Soldering)
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V
in
and V
out
should be constrained to the range V
SS
≤ (V
in
or V
out
) ≤ V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
MARKING DIAGRAMS
SOIC−16 TSSOP−16
14094BG
AWLYWW
14
094B
ALYWG
G
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Indicator
SOEIAJ−16
MC14094B
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
1
16
1
16
1
16
SOIC−16
D SUFFIX
CASE 751B
TSSOP−1
DT SUFFIX
CASE 948
SOEIAJ−16
F SUFFIX
CASE 966
