MC145026MC145027MC145028SC41343SC41344MOTOROLA
13
HAS
THE TRANSMISSION
BEGUN?
NO
YES
YES
YES
NO
NO
DOES
THE ADDRESS
MATCH THE
ADDRESS
PINS?
DISABLE VT ON THE 1ST
ADDRESS MISMATCH
AND IGNORE THE REST
OF THIS WORD
DISABLE VT
IS
THIS AT LEAST
THE 2ND CONSECUTIVE
MATCH SINCE VT
DISABLE?
ACTIVATE VT
HAVE
4–BIT TIMES
PASSED?
HAS A
NEW TRANSMISSION
BEGUN?
YES
YES
NO
NO
Figure 14. MC145028 Flowchart
MC145026MC145027MC145028SC41343SC41344 MOTOROLA
14
MC145027 AND MC145028 TIMING
To verify the MC145027 or MC145028 timing, check the
waveforms on C1 (Pin 7) and R2/C2 (Pin 10) as compared to
the incoming data waveform on D
in
(Pin 9).
The R–C decay seen on C1 discharges down to 1/3 V
DD
before being reset to V
DD
. This point of reset (labelled “DOS”
in Figure 15) is the point in time where the decision is made
whether the data seen on D
in
is a 1 or 0. DOS should not be
too close to the D
in
data edges or intermittent operation may
occur.
The other timing to be checked on the MC145027 and
MC145028 is on R2/C2 (see Figure 16). The R–C decay is
continually reset to V
DD
as data is being transmitted. Only
between words and after the end–of–transmission (EOT)
does R2/C2 decay significantly from V
DD
. R2/C2 can be used
to identify the internal end–of–word (EOW) timing edge which
is generated when R2/C2 decays to 2/3 V
DD
. The internal
EOT timing edge occurs when R2/C2 decays to 1/3 V
DD
.
When the waveform is being observed, the R–C decay
should go down between the 2/3 and 1/3 V
DD
levels, but not
too close to either level before data transmission on D
in
re-
sumes.
Verification of the timing described above should ensure a
good match between the MC145026 transmitter and the
MC145027 and MC145028 receivers.
V
DD
0 V
D
in
V
DD
2/3
1/3
0 V
C1
DOS DOS
Figure 15. R–C Decay on Pin 7 (C1)
V
DD
2/3
1/3
0 V
R2/C2
EOT
Figure 16. R–C Decay on Pin 10 (R2/C2)
EOW
MC145026MC145027MC145028SC41343SC41344MOTOROLA
15
V
DD
TE
5
TRINARY
ADDRESSES
4–BIT
BINARY
DATA
A1
A2
A3
A4
A5
D6
D7
D8
D9
1
2
3
4
5
6
7
9
10
14 16
15 D
out
0.1
µ
F
MC145026
8
12
11
R
TC
R
S
V
DD
13
C
TC
REPEAT OF ABOVE
MC145027
OR
SC41343
V
DD
0.1
µ
F
16
D
in
9
6
7
10
R2
C
2
R1
C
1
1
2
3
4
5
15
14
13
12
11
D6
D7
D8
D9
VT
V
DD
5
TRINARY
ADDRESSES
A1
A2
A3
A4
A5
Figure 17. Typical Application
C
TC
= C
TC
+ C
layout
+ 12 pF
100 pF C
TC
15 µF
R
TC
10 k; R
S
2 R
TC
R
1
10 k
C
1
400 pF
R
2
100 k
C
2
700 pF
f
osc
=
1
2.3 R
TC
C
TC
R
1
C
1
= 3.95 R
TC
C
TC
R
2
C
2
= 77 R
TC
C
TC
Example R/C Values (All Resistors and Capacitors are ± 5%)
(C
TC
= C
TC
+ 20 pF)
f
osc
(kHz) R
TC
C
TC
R
S
R
1
C
1
R
2
C
2
362
181
88.7
42.6
21.5
8.53
1.71
10 k
10 k
10 k
10 k
10 k
10 k
50 k
20 k
20 k
20 k
20 k
20 k
20 k
100 k
120 pF
240 pF
490 pF
1020 pF
2020 pF
5100 pF
5100 pF
10 k
10 k
10 k
10 k
10 k
10 k
50 k
100 k
100 k
100 k
100 k
100 k
200 k
200 k
8
910 pF
1800 pF
3900 pF
7500 pF
0.015 µF
0.02 µF
0.1 µF
470 pF
910 pF
2000 pF
3900 pF
8200 pF
0.02 µF
0.02 µF
REPEAT OF ABOVE

MC145026D

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
Phase Locked Loops - PLL Encoder
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union