DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
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USING THE CLOCK ALARM
The alarm settings and control reside within registers 08h to 0Bh (Table 2). The TIE bit and alarm mask bits AM1 to
AM4 must be set as described below for the IRQ or PWR outputs to be activated for a matched alarm condition.
The alarm functions as long as at least one supply is at a valid level. Note that activating the PWR pin requires the
use of V
BAUX
.
The alarm can be programmed to activate on a specific day of the month, day of the week, or repeat every day,
hour, minute, or second. It can also be programmed to go off while the DS1501/DS1511 are in the battery-backed
state of operation to serve as a system wakeup. Alarm mask bits AM1 to AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once-per-second mode to notify the
user of an incorrect alarm setting. When the RTC register values match alarm register settings, the time-of-
day/date alarm flag TDF bit is set to 1. Once the TDF flag is set, the TIE bit enables the alarm to activate the IRQ
pin. The TPE bit enables the alarm flag to activate the PWR pin. Note that TE must be enabled when a match
occurs for the flags to be set.
Table 3. Alarm Mask Bits
DY/DT AM4 AM3 AM2 AM1 ALARM RATE
X 1 1 1 1 Once per second
X 1 1 1 0 When seconds match
X 1 1 0 0 When minutes and seconds match
X 1 0 0 0 When hours, minutes, and seconds match
0 0 0 0 0 When date, hours, minutes, and seconds match
1 0 0 0 0 When day, hours, minutes, and seconds match
CONTROL REGISTERS
The DS1501/DS1511 controls and status information for the features are maintained in the following register bits.
Month Register (05h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EOSC E32K
BB32 10 Month Month
EOSC, Oscillator Start/Stop Bit (05h Bit 7)
This bit when set to logic 0 starts the oscillator. When this bit is set to logic 1, the oscillator is stopped. This bit is
automatically set to logic 0 by the internal power-on reset when power is applied and V
CC
rises above the power-fail
voltage.
E32K, Enable 32.768kHz Output (05h Bit 6)
This bit, when written to 0, enables the 32.768 kHz oscillator frequency to be output on the SQW pin if the oscillator
is running. This bit is automatically set to logic 0 by the internal power-on reset when power is applied and V
CC
rises above the power-fail voltage.
BB32, Battery Backup 32kHz Enable Bit (05h Bit 5)
When the BB32 bit is written to 1, it enables a 32kHz signal to be output on the SQW pin while the part is in
battery-backup mode, if voltage is applied to V
BAUX.
AM1 to AM4, Alarm Mask Bits (08H Bit 7; 09H Bit 7; 0AH Bit 7; 0BH Bit 7)
Bit 7 of registers 08h to 0Bh contains an alarm mask bit, AM1 to AM4. These bits, in conjunction with the TIE
described later, allow the IRQ output to be activated for a matched-alarm condition. The alarm can be programmed
to activate on a specific day of the month, day of the week, or repeat every day, hour, minute, or second. Table 3
shows the possible settings for AM1 to AM4 and the resulting alarm rates. Configurations not listed in the table
default to the once-per-second mode to notify the user of an incorrect alarm setting.
DY/DT, Day/Date Bit (0BH Bit 6)
The DY/DT bit controls whether the alarm value stored in bits 0 to 5 of 0BH reflects the day of the week or the date
of the month. If DY/DT is written to a 0, the alarm is the result of a match with the date of the month. If DY/DT is
written to a 1, the alarm is the result of a match with the day of the week.
