© 2001 Fairchild Semiconductor Corporation DS500709 www.fairchildsemi.com
November 2001
Revised November 2001
74ALVC162373 Low Voltage 16-Bit Transparent Latch
74ALVC162373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
and 26
Ω Series Resistors in Outputs
General Description
The ALVC162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE
) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
The ALVC162373 is also designed with 26
Ω resistors in
the outputs. This design reduces line noise in applications
such as memory address drivers, clock drivers and bus
transceivers/transmitters.
The 74ALVC162373 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
■ 1.65V to 3.6V V
CC
supply operation
■ 3.6V tolerant inputs and outputs
■ 26
Ω series resistors in outputs
■ t
PD
(I
n
to O
n
)
3.8 ns max for 3.0V to 3.6V V
CC
5.0 ns max for 2.3V to 2.7V V
CC
9.0 ns max for 1.65V to 1.95V V
CC
■ Power-off high impedance inputs and outputs
■ Support live insertion and withdrawal (Note 1)
■ Uses patented noise/EMI reduction circuitry
■ Latchup conforms to JEDEC JED78
■ ESD performance:
Human body model
> 2000V
Machine model
> 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE
should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Ordering Number Package Number Package Description
74ALVC162373T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
LE
n
Latch Enable Input
I
0
–I
15
Inputs
O
0
–O
15
Outputs