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AD7298BCPZ-RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
AD7298
Rev. B | Page 3 of 24
SPECIFICATIONS
V
DD
= 2.8 V to 3.6 V; V
DRIVE
= 1.65 V to 3.6 V; f
SAMPLE
= 1 MSPS, f
SCLK
= 20 MHz, V
REF
= 2.5 V internal; T
A
= −40°C to +125°C, unless
otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f
IN
= 50 kHz sine wave
Signal-to-Noise Ratio (SNR)
1, 2
70 72 dB
Signal-to-Noise (and Distortion) Ratio (SINAD)
1
70 71 dB
Total Harmonic Distortion (THD)
1
−82 −77 dB
Spurious-Free Dynamic Range (SFDR)
−84 −77.5 dB
Intermodulation Distortion (IMD)
f
A
= 40.1 kHz, f
B
= 41.5 kHz
Second-Order Terms −84 dB
Third-Order Terms −93 dB
Channel-to-Channel Isolation −100 dB f
IN
= 50 kHz, f
NOISE
= 60 kHz
SAMPLE AND HOLD
Aperture Delay
3
12 ns
Aperture Jitter
3
40 ps
Full Power Bandwidth 30 MHz @ 3 dB
10 MHz @ 0.1 dB
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity (INL)
1
±0.5 ±1 LSB
Differential Nonlinearity (DNL)
1
±0.5 ±0.99 LSB Guaranteed no missed codes to 12 bits
Offset Error
1
±2 ±4.5 LSB
Offset Error Matching
1
±2.5 ±4.5 LSB
Offset Temperature Drift 4 ppm/°C
Gain Error
1
±1 ±4 LSB
Gain Error Matching
1
±1 ±2.5 LSB
Gain Temperature Drift 0.5 ppm/°C
ANALOG INPUT
Input Voltage Ranges 0 V
REF
V
DC Leakage Current ±0.01 ±1 µA
Input Capacitance 32 pF When in track
8 pF When in hold mode
REFERENCE INPUT/OUTPUT
Reference Output Voltage
4
2.4925 2.5 2.5075 V ±0.3% maximum @ 25°C
Long-Term Stability 150 ppm For 1000 hours
Output Voltage Hysteresis 50 ppm
Reference Input Voltage Range
5
1 2.5 V
DC Leakage Current ±0.01 ±1 µA External reference applied to Pin V
REF
V
REF
Output Impedance 1 Ω
V
REF
Temperature Coefficient 12 35 ppm/°C
V
REF
Noise 60 µV rms Bandwidth = 10 MHz
AD7298
Rev. B | Page 4 of 24
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, V
INH
0.7 × V
DRIVE
V
Input Low Voltage, V
INL
+0.3 × V
DRIVE
V
Input Current, I
IN
±0.01 ±1 µA V
IN
= 0 V or V
DRIVE
Input Capacitance, C
IN
3
3 pF
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DRIVE
− 0.3 V V
DRIVE
< 1.8
V
DRIVE
− 0.2 V V
DRIVE
≥ 1.8
Output Low Voltage, V
OL
0.4 V
Floating State Leakage Current ±0.01 ±1 µA
Floating State Output Capacitance
3
8 pF
INTERNAL TEMPERATURE SENSOR
Operating Range −40 +125
Accuracy ±1 ±2 °C T
A
= −40°C to +85°C
±1 ±3 °C T
A
= +85°C to +125°C
Resolution 0.25 °C LSB size
CONVERSION RATE
Conversion Time 1 t
2
+ 16 × t
SCLK
s For V
IN0
to V
IN7
, with one cycle latency
100 s T
SENSE
temperature sensor channel
Track-and-Hold Acquisition Time
3
100 ns Full-scale step input
Throughput Rate 1 MSPS
f
SCLK
= 20 MHz, for analog voltage
conversions, one cycle latency
10 KSPS For the T
SENSE
channel, one cycle latency
POWER REQUIREMENTS Digital inputs = 0 V or V
DRIVE
V
DD
2.8 3 3.6 V
V
DRIVE
1.65 3 3.6 V
I
TOTAL
6
V
DD
= 3.6 V, V
DRIVE
= 3.6 V
Normal Mode (Operational)
5.8 6.3 mA
Normal Mode (Static) 4.1 4.6 mA
Partial Power-Down Mode 2.7 3.3 mA
Full Power-Down Mode 1 1.6 A T
A
= −40°C to +25°C
10 A T
A
= −40°C to +125°C
Power Dissipation
7
Normal Mode (Operational) 17.4 18.9 mW V
DD
= 3 V, V
DRIVE
= 3 V
22.7 mW
Normal Mode (Static) 14.8 16.6 mW
Partial Power-Down Mode 9.8 11.9 mW
Full Power-Down Mode 3.6 5.8 W T
A
= −40°C to +25°C
36 W T
A
= −40°C to +125°C
1
See the Terminology section.
2
All specifications expressed in decibels are referred to full-scale input, FSR, and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
3
Sample tested during initial release to ensure compliance.
4
Refers to Pin V
REF
specified for 25
o
C.
5
A correction factor may be required on the temperature sensor results when using an external V
REF
(see the Temperature Sensor Averaging section).
6
I
TOTAL
is the total current flowing in V
DD
and V
DRIVE
.
7
Power dissipation is specified with V
DD
= V
DRIVE
= 3.6 V, unless otherwise noted.
AD7298
Rev. B | Page 5 of 24
TIMING SPECIFICATIONS
V
DD
= 2.8 V to 3.6 V; V
DRIVE
= 1.65 V to 3.6 V; V
REF
= 2.5 V internal; T
A
= −40°C to + 125°C, unless otherwise noted. Sample tested during
initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DRIVE
) and timed from a voltage level
of 1.6 V.
Table 2.
Parameter Limit at T
MIN
, T
MAX
Unit Test Conditions/Comments
t
CONVERT
t
2
+ (16 × t
SCLK
) µs max Conversion time
820 ns typ Each ADC channel V
IN0
to V
IN7
, f
SCLK
= 20 MHz
100 µs max Temperature sensor channel
f
SCLK
1
50 kHz min Frequency of external serial clock
20 MHz max Frequency of external serial clock
t
QUIET
6 ns min
Minimum quiet time required between the end of serial read and the start
of the next voltage conversion in repeat and nonrepeat mode.
t
2
10 ns min
CS
to SCLK setup time
t
3
1
15 ns max Delay from CS (falling edge) until DOUT three-state disabled
t
4
1
Data access time after SCLK falling edge
35 ns max V
DRIVE
= 1.65 V to 3 V
28 ns max V
DRIVE
= 3 V to 3.6 V
t
5
0.4 × t
SCLK
ns min SCLK low pulse width
t
6
0.4 × t
SCLK
ns min SCLK high pulse width
t
7
1
14 ns min SCLK to DOUT valid hold time
t
8
1
16/34 ns min/max SCLK falling edge to DOUT high impedance
t
9
5 ns min DIN setup time prior to SCLK falling edge
t
10
4 ns min DIN hold time after SCLK falling edge
t
11
100 ns min
T
SENSE_
BUSY falling edge to CS falling edge
t
12
1
30 ns max
Delay from CS
rising edge to DOUT high impedance
t
POWER-UP_PARTIAL
1 s max Power-up time from partial power-down
t
POWER-UP
6 ms max Internal reference power-up time from full power-down
1
Measured with a load capacitance on DOUT of 15 pF.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD7298BCPZ-RL7

Mfr. #:
Buy AD7298BCPZ-RL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 8-Ch 1 MSPS 10B SAR
Lifecycle:
New from this manufacturer.
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