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LTC4242CUHF#TRPBF

P1-P3P4-P6P7-P9P10-P10
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 1
1 Publication Order Number:
74LVC373A/D
74LVC573A
Low-Voltage CMOS Octal
Transparent Latch
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The 74LVC573A is a high performance, non−inverting octal
transparent latch operating from a 1.2 to 3.6 V supply. High impedance
TTL compatible inputs significantly reduce current loading to input
drivers while TTL compatible outputs offer improved switching noise
performance. A V
I
specification of 5.5 V allows 74LVC573A inputs
to be safely driven from 5 V devices.
The 74LVC573A contains 8 D−type latches with 3−state outputs.
When the Latch Enable (LE) input is HIGH, data on the Dn inputs
enters the latches. In this condition, the latches are transparent, i.e., a
latch output will change state each time its D input changes. When LE
is LOW, the latches store the information that was present on the D
inputs a setup time preceding the HIGH−to−LOW transition of LE.
The 3−state standard outputs are controlled by the Output Enable (OE
)
input. When OE
is LOW, the standard outputs are enabled. When OE
is HIGH, the standard outputs are in the high impedance state, but this
does not interfere with new data entering into the latches.
Features
• Designed for 1.2 to 3.6 V V
CC
Operation
• 5 V Tolerant − Interface Capability With 5 V TTL Logic
• Supports Live Insertion and Withdrawal
• I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
• 24 mA Output Sink and Source Capability
• Near Zero Static Supply Current in all Three Logic States (10 mA)
Substantially Reduces System Power Requirements
• ESD Performance:
♦ Human Body Model >2000 V
♦ Machine Model >200 V
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
1
20
MARKING
DIAGRAM
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
LCX
573A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
1
20
See detailed ordering and shipping information on page 8 o
f
this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
www.onsemi.com
74LVC573A
www.onsemi.com
2
Figure 1. Pinout (Top View)
Figure 2. Logic Diagram
1920 18 17 16 15 14
21 34567
V
CC
13
8
12
9
11
10
O0 O1 O2 O3 O4 O5 O6 O7 LE
OE
D0 D1 D2 D3 D4 D5 D6 D7 GND
O0
D0
O1
D1
O2
D2
O3
D3
O4
D4
O5
D5
O6
D6
O7
D7
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
OE
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
11
1
PIN NAMES
Function
Output Enable Input
Latch Enable Input
Data Inputs
3−State Latch Outputs
Pins
OE
LE
D0−D7
O0−O7
TRUTH TABLE
Inputs Outputs
Operating Mode
OE LE Dn On
L
L
H
H
H
L
H
L
Transparent (Latch Disabled); Read Latch
L
L
L
L
h
l
H
L
Latched (Latch Enabled) Read Latch
L L X NC Hold; Read Latch
H L X Z Hold; Disabled Outputs
H
H
H
H
H
L
Z
Z
Transparent (Latch Disabled); Disabled Outputs
H
H
L
L
h
l
Z
Z
Latched (Latch Enabled); Disabled Outputs
H = High Voltage Level
h = High Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition
L = Low Voltage Level
l = Low Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition
NC = No Change, State Prior to the Latch Enable High−to−Low Transition
X = High or Low Voltage Level or Transitions are Acceptable
Z = High Impedance State
For I
CC
Reasons DO NOT FLOAT Inputs
74LVC573A
www.onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Condition Value Unit
VCC
DC Supply Voltage −0.5 to +6.5 V
V
I
DC Input Voltage −0.5 ≤ V
I
≤ +6.5 V
V
O
DC Output Voltage
Output in 3−State −0.5 ≤ V
O
≤ +6.5 V
Output in HIGH or LOW State
(Note 1)
−0.5 ≤ V
O
≤ V
CC
+ 0.5 V
IIK
DC Input Diode Current V
I
< GND −50 mA
IOK
DC Output Diode Current
V
O
< GND −50 mA
V
O
> V
CC
+50 mA
I
O
DC Output Source/Sink Current ±50 mA
ICC
DC Supply Current Per Supply Pin ±100 mA
IGND
DC Ground Current Per Ground Pin ±100 mA
TSTG
Storage Temperature Range −65 to +150 °C
T
L
Lead Temperature, 1 mm from Case for
10 Seconds
T
L
= 260 °C
T
J
Junction Temperature Under Bias T
J
= 135 °C
qJA
Thermal Resistance (Note 2) 110.7 °C/W
MSL Moisture Sensitivity Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
O
absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage Operating Functional
1.65
1.2
3.6
3.6
V
V
I
Input Voltage 0 5.5 V
V
O
Output Voltage
HIGH or LOW State
3−State
0
0
V
CC
5.5
V
I
OH
HIGH Level Output Current
V
CC
= 3.0 V − 3.6 V V
CC
= 2.7 V − 3.0 V
−24
−12
mA
I
OL
LOW Level Output Current
V
CC
= 3.0 V − 3.6 V V
CC
= 2.7 V − 3.0 V
24
12
mA
T
A
Operating Free−Air Temperature −40 +125 °C
Dt/DV
Input Transition Rise or Fall Rate,
V
CC
= 1.65 to 2.7 V
V
CC
= 2.7 to 3.6 V
0
0
20
10
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
P1-P3P4-P6P7-P9P10-P10

LTC4242CUHF#TRPBF

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Buy LTC4242CUHF#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Dual PCI Express Hot Swap Controller
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