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PCA9551BS,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
PCA9551_8 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 08 — 31 July 2008 7 of 26
NXP Semiconductors
PCA9551
8-bit I
2
C-bus LED driver with programmable blink rates
6.3.6 LS0 to LS1 - LED selector registers
The LSn LED select registers determine the source of the LED data.
00 = output is set LOW (LED on)
01 = output is set high-impedance (LED off; default)
10 = output blinks at PWM0 rate
11 = output blinks at PWM1 rate
6.4 Pins used as GPIOs
LED pins not used to control LEDs can be used as general purpose I/Os (GPIOs).
For use as input, set LEDn to high-impedance (01) and then read the pin state via the
Input register.
For use as output, connect external pull-up resistor to the pin and size it according to the
DC recommended operating characteristics. LEDn output pin is HIGH when the output is
programmed as high-impedance, and LOW when the output is programmed LOW through
the ‘LED selector’ register. The output can be pulse-width controlled when PWM0 or
PWM1 are used.
6.5 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9551 in
a reset condition until V
DD
has reached V
POR
. At that point, the reset condition is released
and the PCA9551 registers are initialized to their default states, all the outputs in the
OFF state. Thereafter, V
DD
must be lowered below 0.2 V to reset the device.
6.6 External RESET
A reset can be accomplished by holding the RESET pin LOW for a minimum of t
w(rst)
. The
PCA9551 registers and I
2
C-bus state machine will be held in their default states until the
RESET input is once again HIGH.
This input requires a pull-up resistor to V
DD
if no active connection is used.
Table 9. LS0 to LS1 - LED selector registers bit description
Legend: * default value.
Register Bit Value Description
LS0 - LED0 to LED3 selector
LS0 7:6 01* LED3 selected
5:4 01* LED2 selected
3:2 01* LED1 selected
1:0 01* LED0 selected
LS1 - LED4 to LED7 selector
LS1 7:6 01* LED7 selected
5:4 01* LED6 selected
3:2 01* LED5 selected
1:0 01* LED4 selected
PCA9551_8 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 08 — 31 July 2008 8 of 26
NXP Semiconductors
PCA9551
8-bit I
2
C-bus LED driver with programmable blink rates
7. Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 7).
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 8).
7.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 9).
Fig 7. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 8. Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
PCA9551_8 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 08 — 31 July 2008 9 of 26
NXP Semiconductors
PCA9551
8-bit I
2
C-bus LED driver with programmable blink rates
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 9. System configuration
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I
2
C-BUS
MULTIPLEXER
SLAVE
Fig 10. Acknowledgement on the I
2
C-bus
002aaa987
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
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PCA9551BS,118

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Buy PCA9551BS,118
Manufacturer:
NXP Semiconductors
Description:
LED Lighting Drivers 8-BIT I2C FM OD LED
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