NCV8770
http://onsemi.com
10
APPLICATIONS INFORMATION
The NCV8770 regulator is self−protected with internal
thermal shutdown and internal current limit. Typical
characteristics are shown in Figure 4 to Figure 21.
Input Decoupling (C
in
)
A ceramic or tantalum 0.1 mF capacitor is recommended
and should be connected close to the NCV8770 package.
Higher capacitance and lower ESR will improve the overall
line and load transient response.
If extremely fast input voltage transients are expected then
appropriate input filter must be used in order to decrease
rising and/or falling edges below 50 V/ms for proper
operation. The filter can be composed of several capacitors
in parallel.
Output Decoupling (C
out
)
The NCV8770 is a stable component and does not require
a minimum Equivalent Series Resistance (ESR) for the
output capacitor. Stability region of ESR vs Output Current
is shown in Figure 13. The minimum output decoupling
value is 1 mF and can be augmented to fulfill stringent load
transient requirements. The regulator works with ceramic
chip capacitors as well as tantalum devices. Larger values
improve noise rejection and load regulation transient
response.
Reset Operation
A reset signal is provided on the Reset Output (RO) pin to
provide feedback to the microprocessor of an out of
regulation condition. The timing diagram of reset function
is shown in Figure 21. This is in the form of a logic signal on
RO. Output voltage conditions below the RESET threshold
cause RO to go low. The RO integrity is maintained down
to V
out
= 1.0 V. For 5 V voltage option, the Reset Output
(RO) circuitry includes internal pull−up (30 kW) connected
to the output (V
out
) No external pull−up is necessary.
Reset Delay Time Select
Selection of the NCV8770y devices and the state of the
DT pin determines the available Reset Delay times. The part
is designed for use with DT tied to ground or V
out
, but may
be controlled by any logic signal which provides a threshold
between 0.8 V and 2 V. The default condition for an open DT
pin is the slower Reset time (DT = GND condition). Times
are in pairs and are highlighted in the chart below. Consult
factory for availability. The Delay Time select (DT) pin is
logic level controlled and provides Reset Delay time per the
chart. Note the DT pin is sampled only when RO is low, and
changes to the DT pin when RO is high will not effect the
reset delay time.
RESET DELAY AND RESET THRESHOLD OPTIONS
DT = GND
Reset
Time
DT = V
out
Reset
Time
Reset
Threshold
NCV87701 8 ms 128 ms 93%
NCV87702 8 ms 32 ms 93%
NCV87703 16 ms 64 ms 93%
NCV87704 32 ms 128 ms 93%
NCV87705 4 ms 8 ms 93%
NCV87706 16 ms 128 ms 93%
NCV8770A 8 ms 128 ms 90%
NCV8770B 8 ms 32 ms 90%
NCV8770C 16 ms 64 ms 90%
NCV8770D 32 ms 128 ms 90%
NCV8770E 4 ms 8 ms 90%
NCV8770F 16 ms 128 ms 90%
NOTE: The timing values can be selected from the following list:
4, 8, 16, 32, 64, 128 ms. Contact factory for options not
included in ORDERING INFORMATION table on
following page.
Thermal Considerations
As power in the NCV8770 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCV8770 has good thermal conductivity through the
PCB, the junction temperature will be relatively low with
high power applications. The maximum dissipation the
NCV8770 can handle is given by:
P
D
(
max
)
+
ƪ
T
J(max)
* T
A
ƫ
R
qJA
(eq. 1)
Since T
J
is not recommended to exceed 150°C, then the
NCV8770 soldered on 645 mm
2
, 1 oz copper area, FR4 can
dissipate up to 2.35 W (for D2PAK−5) when the ambient
temperature (T
A
) is 25°C. See Figure 22 for R
q
JA
versus
PCB area. The power dissipated by the NCV8770 can be
calculated from the following equations:
P
D
+ V
in
ǒ
I
q
@I
out
Ǔ
) I
out
ǒ
V
in
* V
out
Ǔ
(eq. 2)
or
V
in(max)
+
P
D(max)
)
ǒ
V
out
I
out
Ǔ
I
out
) I
q
(eq. 3)
NOTE: Items containing I
q
can be neglected if I
out
>> I
q
.
