7©2015 Integrated Device Technology, Inc December 16, 2015
83052I-01 Datasheet
Table 5E. AC Characteristics, V
DD
= 2.5V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
=-40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same input on each device, the output is measured at V
DDO
/2.
NOTE 5: Driving only one input clock.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low to High;
NOTE 1
2.0 3.1 4.2 ns
tp
HL
Propagation Delay, High to Low;
NOTE 1
2.0 3.1 4.2 ns
tsk(i) Input Skew; NOTE 2 30 135 ps
tsk(o) Output Skew; NOTE 2, 3 30 95 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 500 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
section, NOTE 5
Integration Range: 12kHz - 20MHz 0.17 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 150 1000 ps
odc Output Duty Cycle 40 60 %
MUX
ISOL
MUX Isolation Unselected CLK input @100MHz 45 dB
8©2015 Integrated Device Technology, Inc December 16, 2015
83052I-01 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.15ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
9©2015 Integrated Device Technology, Inc December 16, 2015
83052I-01 Datasheet
Parameter Measurement Information
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
3.3V Core/ 1.8V LVCMOS Output Load AC Test Circuit
2.5V Core/ 1.8V LVCMOS Output Load AC Test Circuit
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
2.5V Core/ 2.5V LVCMOS Output Load AC Test Circuit
Propagation Delay
SCOPE
Qx
GND
V
DD,
1.65V±5%
-1.65V±5%
V
DDO
SCOPE
Qx
GND
2.4V±0.65V
-0.9V±0.1V
0.9V±0.1V
V
DDO
V
DD
SCOPE
Qx
GND
V
DDO
V
DD
1.6V±0.025V
0.9V±0.1V
-0.9V±0.1V
SCOPE
Qx
GND
V
DDO
V
DD
1.25V±5%
-1.25V±5%
2.05V±5%
SCOPE
Qx
GND
1.25V±5%
-1.25V±5%
V
DD,
V
DDO
tp
LH
tp
HL
V
DDO
2
V
DD
2
V
DDO
2
V
DD
2
Q0, Q1
CLK0, CLK1

83052AGI-01LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2 BIT 2:1 SINGLE END
Lifecycle:
New from this manufacturer.
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