SX Family FPGAs
v3.2 1-13
A54SX16P AC Specifications (3.3 V PCI Operation)
Table 1-9 • A54SX16P AC Specifications (3.3 V PCI Operation)
Symbol Parameter Condition Min. Max. Units
I
OH(AC)
Switching Current High 0 < V
OUT
≤ 0.3V
CC
1
mA
0.3V
CC
≤ V
OUT
< 0.9V
CC
1
–12V
CC
mA
0.7V
CC
< V
OUT
< V
CC
1, 2
–17.1 + (V
CC
– V
OUT
) EQ 1-3 on page 1-14
(Test Point) V
OUT
= 0.7V
CC
2
–32V
CC
mA
I
OL(AC)
Switching Current High V
CC
> V
OUT
≥ 0.6V
CC
1
mA
0.6V
CC
> V
OUT
> 0.1V
CC
1
16V
CC
mA
0.18V
CC
> V
OUT
> 0
1, 2
26.7V
OUT
EQ 1-4 on page 1-14 mA
(Test Point) V
OUT
= 0.18V
CC
2
38V
CC
I
CL
Low Clamp Current –3 < V
IN
≤ –1 –25 + (V
IN
+ 1)/0.015 mA
I
CH
High Clamp Current –3 < V
IN
≤ –1 25 + (V
IN
– V
OUT
– 1)/0.015 mA
slew
R
Output Rise Slew Rate
3
0.2V
CC
to 0.6V
CC
load 1 4 V/ns
slew
F
Output Fall Slew Rate
3
0.6V
CC
to 0.2V
CC
load 1 4 V/ns
Notes:
1. Refer to the V/I curves in Figure 1-10 on page 1-14. Switching current characteristics for REQ# and GNT# are permitted to be
one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to
CLK and RST# which are system outputs. “Switching Current High” specification are not relevant to SERR#, INTA#, INTB#,
INTC#, and INTD# which are open drain outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums
(C and D) are provided with the respective diagrams in Figure 1-10 on page 1-14. The equation defined maxima should be
met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output
driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate
at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet
this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both
maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply
to open drain outputs.
1/2 in. max.
Pin
Output
Buffer
V
CC
10 pF
1 kΩ
1 kΩ
