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A54SX16-2TQG176I

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64
SX Family FPGAs
v3.2 1-27
Dedicated (Hardwired) Array Clock Network
t
HCKH
Input LOW to HIGH (pad to R-Cell input) 1.2 1.4 1.5 1.8 ns
t
HCKL
Input HIGH to LOW (pad to R-Cell input) 1.2 1.4 1.6 1.9 ns
t
HPWH
Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 ns
t
HPWL
Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 ns
t
HCKSW
Maximum Skew 0.2 0.2 0.3 0.3 ns
t
HP
Minimum Period 2.7 3.1 3.6 4.2 ns
f
HMAX
Maximum Frequency 350 320 280 240 MHz
Routed Array Clock Networks
t
RCKH
Input LOW to HIGH (light load)
(pad to R-Cell input)
1.61.82.12.5ns
t
RCKL
Input HIGH to LOW (light load)
(pad to R-Cell input)
1.82.02.32.7ns
t
RCKH
Input LOW to HIGH (50% load)
(pad to R-Cell input)
1.82.12.52.8ns
t
RCKL
Input HIGH to LOW (50% load)
(pad to R-Cell input)
2.02.22.53.0ns
t
RCKH
Input LOW to HIGH (100% load)
(pad to R-Cell input)
1.82.12.42.8ns
t
RCKL
Input HIGH to LOW (100% load)
(pad to R-Cell input)
2.02.22.53.0ns
t
RPWH
Min. Pulse Width HIGH 2.1 2.4 2.7 3.2 ns
t
RPWL
Min. Pulse Width LOW 2.1 2.4 2.7 3.2 ns
t
RCKSW
Maximum Skew (light load) 0.5 0.5 0.5 0.7 ns
t
RCKSW
Maximum Skew (50% load) 0.5 0.6 0.7 0.8 ns
t
RCKSW
Maximum Skew (100% load) 0.5 0.6 0.7 0.8 ns
TTL Output Module Timing
3
t
DLH
Data-to-Pad LOW to HIGH 1.6 1.9 2.1 2.5 ns
t
DHL
Data-to-Pad HIGH to LOW 1.6 1.9 2.1 2.5 ns
t
ENZL
Enable-to-Pad, Z to L 2.1 2.4 2.8 3.2 ns
t
ENZH
Enable-to-Pad, Z to H 2.3 2.7 3.1 3.6 ns
t
ENLZ
Enable-to-Pad, L to Z 1.4 1.7 1.9 2.2 ns
t
ENHZ
Enable-to-Pad, H to Z 1.3 1.5 1.7 2.0 ns
Table 1-18 • A54SX16 Timing Characteristics (Continued)
(Worst-Case Commercial Conditions, V
CCR
= 4.75 V, V
CCA
,V
CCI
= 3.0 V, T
J
= 70°C)
Parameter Description
'–3' Speed '–2' Speed '–1' Speed 'Std' Speed
Min. Max. Min. Max. Min. Max. Min. Max. Units
Notes:
1. For dual-module macros, use t
PD
+ t
RD1
+ t
PDn
, t
RCO
+ t
RD1
+ t
PDn,
or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Delays based on 35 pF loading, except t
ENZL
and t
ENZH
. For t
ENZL
and t
ENZH,
the loading is 5 pF.
SX Family FPGAs
1-28 v3.2
A54SX16P Timing Characteristics
Table 1-19 • A54SX16P Timing Characteristics
(Worst-Case Commercial Conditions, V
CCR
= 4.75 V, V
CCA
,V
CCI
= 3.0 V, T
J
= 70°C)
Parameter Description
'–3' Speed '–2' Speed '–1' Speed 'Std' Speed
Min. Max. Min. Max. Min. Max. Min. Max. Units
C-Cell Propagation Delays
1
t
PD
Internal Array Module 0.6 0.7 0.8 0.9 ns
Predicted Routing Delays
2
t
DC
FO = 1 Routing Delay, Direct Connect 0.1 0.1 0.1 0.1 ns
t
FC
FO = 1 Routing Delay, Fast Connect 0.3 0.4 0.4 0.5 ns
t
RD1
FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns
t
RD2
FO = 2 Routing Delay 0.6 0.7 0.8 0.9 ns
t
RD3
FO = 3 Routing Delay 0.8 0.9 1.0 1.2 ns
t
RD4
FO = 4 Routing Delay 1.0 1.2 1.4 1.6 ns
t
RD8
FO = 8 Routing Delay 1.9 2.2 2.5 2.9 ns
t
RD12
FO = 12 Routing Delay 2.8 3.2 3.7 4.3 ns
R-Cell Timing
t
RCO
Sequential Clock-to-Q 0.9 1.1 1.3 1.4 ns
t
CLR
Asynchronous Clear-to-Q 0.5 0.6 0.7 0.8 ns
t
PRESET
Asynchronous Preset-to-Q 0.7 0.8 0.9 1.0 ns
t
SUD
Flip-Flop Data Input Set-Up 0.5 0.5 0.7 0.8 ns
t
HD
Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 ns
t
WASYN
Asynchronous Pulse Width 1.4 1.6 1.8 2.1 ns
Input Module Propagation Delays
t
INYH
Input Data Pad-to-Y HIGH 1.5 1.7 1.9 2.2 ns
t
INYL
Input Data Pad-to-Y LOW 1.5 1.7 1.9 2.2 ns
Predicted Input Routing Delays
2
t
IRD1
FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns
t
IRD2
FO = 2 Routing Delay 0.6 0.7 0.8 0.9 ns
t
IRD3
FO = 3 Routing Delay 0.8 0.9 1.0 1.2 ns
t
IRD4
FO = 4 Routing Delay 1.0 1.2 1.4 1.6 ns
t
IRD8
FO = 8 Routing Delay 1.9 2.2 2.5 2.9 ns
t
IRD12
FO = 12 Routing Delay 2.8 3.2 3.7 4.3 ns
Note:
1. For dual-module macros, use t
PD
+ t
RD1
+ t
PDn
, t
RCO
+ t
RD1
+ t
PDn,
or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Delays based on 10 pF loading.
SX Family FPGAs
v3.2 1-29
Dedicated (Hardwired) Array Clock Network
t
HCKH
Input LOW to HIGH (pad to R-Cell input) 1.2 1.4 1.5 1.8 ns
t
HCKL
Input HIGH to LOW (pad to R-Cell input) 1.2 1.4 1.6 1.9 ns
t
HPWH
Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 ns
t
HPWL
Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 ns
t
HCKSW
Maximum Skew 0.2 0.2 0.3 0.3 ns
t
HP
Minimum Period 2.7 3.1 3.6 4.2 ns
f
HMAX
Maximum Frequency 350 320 280 240 MHz
Routed Array Clock Networks
t
RCKH
Input LOW to HIGH (light load)
(pad to R-Cell input)
1.61.82.12.5ns
t
RCKL
Input HIGH to LOW (Light Load)
(pad to R-Cell input)
1.82.02.32.7ns
t
RCKH
Input LOW to HIGH (50% load)
(pad to R-Cell input)
1.82.12.52.8ns
t
RCKL
Input HIGH to LOW (50% load)
(pad to R-Cell input)
2.02.22.53.0ns
t
RCKH
Input LOW to HIGH (100% load)
(pad to R-Cell input)
1.82.12.42.8ns
t
RCKL
Input HIGH to LOW (100% load)
(pad to R-Cell input)
2.02.22.53.0ns
t
RPWH
Min. Pulse Width HIGH 2.1 2.4 2.7 3.2 ns
t
RPWL
Min. Pulse Width LOW 2.1 2.4 2.7 3.2 ns
t
RCKSW
Maximum Skew (light load) 0.5 0.5 0.5 0.7 ns
t
RCKSW
Maximum Skew (50% load) 0.5 0.6 0.7 0.8 ns
t
RCKSW
Maximum Skew (100% load) 0.5 0.6 0.7 0.8 ns
TTL Output Module Timing
t
DLH
Data-to-Pad LOW to HIGH 2.4 2.8 3.1 3.7 ns
t
DHL
Data-to-Pad HIGH to LOW 2.3 2.9 3.2 3.8 ns
t
ENZL
Enable-to-Pad, Z to L 3.0 3.4 3.9 4.6 ns
t
ENZH
Enable-to-Pad, Z to H 3.3 3.8 4.3 5.0 ns
t
ENLZ
Enable-to-Pad, L to Z 2.3 2.7 3.0 3.5 ns
t
ENHZ
Enable-to-Pad, H to Z 2.8 3.2 3.7 4.3 ns
Table 1-19 • A54SX16P Timing Characteristics (Continued)
(Worst-Case Commercial Conditions, V
CCR
= 4.75 V, V
CCA
,V
CCI
= 3.0 V, T
J
= 70°C)
Parameter Description
'–3' Speed '–2' Speed '–1' Speed 'Std' Speed
Min. Max. Min. Max. Min. Max. Min. Max. Units
Note:
1. For dual-module macros, use t
PD
+ t
RD1
+ t
PDn
, t
RCO
+ t
RD1
+ t
PDn,
or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Delays based on 10 pF loading.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64

A54SX16-2TQG176I

Mfr. #:
Buy A54SX16-2TQG176I
Manufacturer:
Microchip / Microsemi
Description:
FPGA - Field Programmable Gate Array SX
Lifecycle:
New from this manufacturer.
Delivery:
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