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A54SX16P-TQG176

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64
SX Family FPGAs
1-18 v3.2
Step 3: Calculate DC Power Dissipation
DC Power Dissipation
P
DC
= (I
standby
) × V
CCA
+ (I
standby
) × V
CCR
+ (I
standby
) ×
V
CCI
+ X × V
OL
× I
OL
+ Y(V
CCI
– V
OH
) × V
OH
EQ 1-12
For a rough estimate of DC Power Dissipation, only use
P
DC
=(I
standby
) × V
CCA
. The rest of the formula provides a
very small number that can be considered negligible.
P
DC
= (I
standby
) × V
CCA
P
DC
= .55 mA × 3.3 V
P
DC
= 0.001815 W
Step 4: Calculate Total Power Consumption
P
Tot a l
= P
AC
+ P
DC
P
Tot a l
= 1.461 + 0.001815
P
Tot a l
= 1.4628 W
Step 5: Compare Estimated Power Consumption
against Characterized Power Consumption
The estimated total power consumption for this design is
1.46 W. The characterized power consumption for this
design at 200 MHz is 1.0164 W.
Step 1: Define Terms Used in Formula
V
CCA
3.3
Module
Number of logic modules switching
at f
m
(Used 50%)
m 264
Average logic modules switching rate
f
m
(MHz) (Guidelines: f/10)
f
m
20
Module capacitance C
EQM
(pF) C
EQM
4.0
Input Buffer
Number of input buffers switching at f
n
n1
Average input switching rate f
n
(MHz)
(Guidelines: f/5)
f
n
40
Input buffer capacitance C
EQI
(pF) C
EQI
3.4
Output Buffer
Number of output buffers switching at f
p
p1
Average output buffers switching rate
f
p
(MHz) (Guidelines: f/10)
f
p
20
Output buffers buffer capacitance
C
EQO
(pF)
C
EQO
4.7
Output Load capacitance C
L
(pF) C
L
35
RCLKA
Number of Clock loads q
1
q
1
528
Capacitance of routed array clock (pF) C
EQCR
1.6
Average clock rate (MHz) f
q1
200
Fixed capacitance (pF) r
1
138
RCLKB
Number of Clock loads q
2
q
2
0
Capacitance of routed array clock (pF) C
EQCR
1.6
Average clock rate (MHz) f
q2
0
Fixed capacitance (pF) r
2
138
HCLK
Number of Clock loads s
1
0
Variable capacitance of dedicated
array clock (pF)
C
EQHV
0.61
5
Fixed capacitance of dedicated
array clock (pF)
C
EQHF
96
Average clock rate (MHz) f
s1
0
Step 2: Calculate Dynamic Power Consumption
V
CCA
× V
CCA
10.89
m × f
m
× C
EQM
0.02112
n × f
n
× C
EQI
0.000136
p × f
p
× (C
EQO
+C
L
) 0.000794
0.5 (q
1
× C
EQCR
× f
q1
) + (r
1
× f
q1
) 0.11208
0.5(q
2
× C
EQCR
× f
q2
) + (r
2
× f
q2
)0
0.5 (s
1
× C
EQHV
× f
s1
) + (C
EQHF
× f
s1
)0
P
AC
= 1.461 W
SX Family FPGAs
v3.2 1-19
Figure 1-11 shows the characterized power dissipation numbers for the shift register design using frequencies ranging
from 1 MHz to 200 MHz.
Junction Temperature (T
J
)
The temperature that you select in Designer Series
software is the junction temperature, not ambient
temperature. This is an important distinction because the
heat generated from dynamic power consumption is
usually hotter than the ambient temperature. Use the
equation below to calculate junction temperature.
Junction Temperature = ΔT + T
a
EQ 1-13
Where:
T
a
= Ambient Temperature
ΔT = Temperature gradient between junction (silicon)
and ambient
ΔT =
θ
ja
× P
P = Power calculated from Estimating Power
Consumption section
θ
ja
= Junction to ambient of package. θ
ja
numbers are
located in the "Package Thermal Characteristics"
section.
Package Thermal Characteristics
The device junction to case thermal characteristic is θ
jc
,
and the junction to ambient air characteristic is θ
ja
. The
thermal characteristics for θ
ja
are shown with two
different air flow rates.
The maximum junction temperature is 150 °C.
A sample calculation of the absolute maximum power
dissipation allowed for a TQFP 176-pin package at
commercial temperature and still air is as follows:
EQ 1-14
Figure 1-11 • Power Dissipation
0
200
400
600
800
1000
1200
Frequency MHz
Power Dissipation mW
200 40 60 80 100 120 140 160 180 200
Maximum Power Allowed
Max. junction temp. (°C) – Max. ambient temp. (°C)
θ
ja
(°C/W)
------------------------------------------------------------------------------------------------------------------------------------
150°C – 70°C
28°C/W
----------------------------------- 2 . 8 6 W===
SX Family FPGAs
1-20 v3.2
Table 1-15 • Package Thermal Characteristics
Package Type Pin Count θ
jc
θ
ja
Still Air
θ
ja
300 ft/min. Units
Plastic Leaded Chip Carrier (PLCC) 84 12 32 22 °C/W
Thin Quad Flat Pack (TQFP) 144 11 32 24 °C/W
Thin Quad Flat Pack (TQFP) 176 11 28 21 °C/W
Very Thin Quad Flatpack (VQFP) 100 10 38 32 °C/W
Plastic Quad Flat Pack (PQFP) without Heat Spreader 208 8 30 23 °C/W
Plastic Quad Flat Pack (PQFP) with Heat Spreader 208 3.8 20 17 °C/W
Plastic Ball Grid Array (PBGA) 272 3 20 14.5 °C/W
Plastic Ball Grid Array (PBGA) 313 3 23 17 °C/W
Plastic Ball Grid Array (PBGA) 329 3 18 13.5 °C/W
Fine Pitch Ball Grid Array (FBGA) 144 3.8 38.8 26.7 °C/W
Note: SX08 does not have a heat spreader.
Table 1-16 • Temperature and Voltage Derating Factors*
V
CCA
Junction Temperature
–55–400 257085125
3.0 0.75 0.78 0.87 0.89 1.00 1.04 1.16
3.3 0.70 0.73 0.82 0.83 0.93 0.97 1.08
3.6 0.66 0.69 0.77 0.78 0.87 0.92 1.02
Note: *Normalized to worst-case commercial, T
J
= 70°C, V
CCA
= 3.0 V
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64

A54SX16P-TQG176

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Buy A54SX16P-TQG176
Manufacturer:
Microchip / Microsemi
Description:
FPGA - Field Programmable Gate Array SX
Lifecycle:
New from this manufacturer.
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