SX Family FPGAs
1-26 v3.2
A54SX16 Timing Characteristics
Table 1-18 • A54SX16 Timing Characteristics
(Worst-Case Commercial Conditions, V
CCR
= 4.75 V, V
CCA
,V
CCI
= 3.0 V, T
J
= 70°C)
Parameter Description
'–3' Speed '–2' Speed '–1' Speed 'Std' Speed
Min. Max. Min. Max. Min. Max. Min. Max. Units
C-Cell Propagation Delays
1
t
PD
Internal Array Module 0.6 0.7 0.8 0.9 ns
Predicted Routing Delays
2
t
DC
FO = 1 Routing Delay, Direct Connect 0.1 0.1 0.1 0.1 ns
t
FC
FO = 1 Routing Delay, Fast Connect 0.3 0.4 0.4 0.5 ns
t
RD1
FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns
t
RD2
FO = 2 Routing Delay 0.6 0.7 0.8 0.9 ns
t
RD3
FO = 3 Routing Delay 0.8 0.9 1.0 1.2 ns
t
RD4
FO = 4 Routing Delay 1.0 1.2 1.4 1.6 ns
t
RD8
FO = 8 Routing Delay 1.9 2.2 2.5 2.9 ns
t
RD12
FO = 12 Routing Delay 2.8 3.2 3.7 4.3 ns
R-Cell Timing
t
RCO
Sequential Clock-to-Q 0.8 1.1 1.2 1.4 ns
t
CLR
Asynchronous Clear-to-Q 0.5 0.6 0.7 0.8 ns
t
PRESET
Asynchronous Preset-to-Q 0.7 0.8 0.9 1.0 ns
t
SUD
Flip-Flop Data Input Set-Up 0.5 0.5 0.7 0.8 ns
t
HD
Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 ns
t
WASYN
Asynchronous Pulse Width 1.4 1.6 1.8 2.1 ns
Input Module Propagation Delays
t
INYH
Input Data Pad-to-Y HIGH 1.5 1.7 1.9 2.2 ns
t
INYL
Input Data Pad-to-Y LOW 1.5 1.7 1.9 2.2 ns
Predicted Input Routing Delays
2
t
IRD1
FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns
t
IRD2
FO = 2 Routing Delay 0.6 0.7 0.8 0.9 ns
t
IRD3
FO = 3 Routing Delay 0.8 0.9 1.0 1.2 ns
t
IRD4
FO = 4 Routing Delay 1.0 1.2 1.4 1.6 ns
t
IRD8
FO = 8 Routing Delay 1.9 2.2 2.5 2.9 ns
t
IRD12
FO = 12 Routing Delay 2.8 3.2 3.7 4.3 ns
Notes:
1. For dual-module macros, use t
PD
+ t
RD1
+ t
PDn
, t
RCO
+ t
RD1
+ t
PDn,
or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Delays based on 35 pF loading, except t
ENZL
and t
ENZH
. For t
ENZL
and t
ENZH,
the loading is 5 pF.