SX Family FPGAs
1-16 v3.2
Evaluating Power in SX Devices
A critical element of system reliability is the ability of
electronic devices to safely dissipate the heat generated
during operation. The thermal characteristics of a circuit
depend on the device and package used, the operating
temperature, the operating current, and the system's
ability to dissipate heat.
You should complete a power evaluation early in the
design process to help identify potential heat-related
problems in the system and to prevent the system from
exceeding the device’s maximum allowed junction
temperature.
The actual power dissipated by most applications is
significantly lower than the power the package can
dissipate. However, a thermal analysis should be
performed for all projects. To perform a power
evaluation, follow these steps:
1. Estimate the power consumption of the
application.
2. Calculate the maximum power allowed for the
device and package.
3. Compare the estimated power and maximum
power values.
Estimating Power Consumption
The total power dissipation for the SX family is the sum
of the DC power dissipation and the AC power
dissipation. Use EQ 1-5 to calculate the estimated power
consumption of your application.
P
Tot a l
= P
DC
+ P
AC
EQ 1-5
DC Power Dissipation
The power due to standby current is typically a small
component of the overall power. The Standby power is
shown in Table 1-12 for commercial, worst-case
conditions (70°C).
The DC power dissipation is defined in EQ 1-6.
P
DC
= (I
standby
) × V
CCA
+ (I
standby
) × V
CCR
+
(I
standby
) × V
CCI
+ xV
OL
× I
OL
+ y(V
CCI
– V
OH
) × V
OH
EQ 1-6
AC Power Dissipation
The power dissipation of the SX Family is usually
dominated by the dynamic power dissipation. Dynamic
power dissipation is a function of frequency, equivalent
capacitance, and power supply voltage. The AC power
dissipation is defined in EQ 1-7 and EQ 1-8.
P
AC
= P
Module
+ P
RCLKA Net
+ P
RCLKB Net
+ P
HCLK Net
+
P
Output Buffer
+ P
Input Buffer
EQ 1-7
P
AC
= V
CCA
2
× [(m × C
EQM
× f
m
)
Module
+
(n × C
EQI
× f
n
)
Input Buffer
+ (p × (C
EQO
+ C
L
) × f
p
)
Output Buffer
+
(0.5 × (q
1
× C
EQCR
× f
q1
) + (r
1
× f
q1
))
RCLKA
+
(0.5 × (q2 × CEQCR × f
q2
)+ (r2 × f
q2
))RCLKB +
(0.5 × (s
1
× C
EQHV
× f
s1
) + (C
EQHF
× f
s1
))
HCLK
]
EQ 1-8
Definition of Terms Used in Formula
m = Number of logic modules switching at f
m
n = Number of input buffers switching at f
n
p = Number of output buffers switching at f
p
q
1
= Number of clock loads on the first routed array
clock
q
2
= Number of clock loads on the second routed array
clock
x = Number of I/Os at logic low
y = Number of I/Os at logic high
r
1
= Fixed capacitance due to first routed array clock
r
2
= Fixed capacitance due to second routed array
clock
s
1
= Number of clock loads on the dedicated array
clock
C
EQM
= Equivalent capacitance of logic modules in pF
C
EQI
= Equivalent capacitance of input buffers in pF
C
EQO
= Equivalent capacitance of output buffers in pF
C
EQCR
= Equivalent capacitance of routed array clock in pF
C
EQHV
= Variable capacitance of dedicated array clock
C
EQHF
= Fixed capacitance of dedicated array clock
C
L
= Output lead capacitance in pF
f
m
= Average logic module switching rate in MHz
f
n
= Average input buffer switching rate in MHz
f
p
= Average output buffer switching rate in MHz
f
q1
= Average first routed array clock rate in MHz
f
q2
= Average second routed array clock rate in MHz
f
s1
= Average dedicated array clock rate in MHz
Table 1-12 • Standby Power
I
CC
V
CC
Power
4 mA 3.6 V 14.4 mW
