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SDP1300Q38CB

P1-P3P4-P5
30
SIDACtor
®
Protection Thyristors
© 2009 Littelfuse, Inc.
Specifications are subject to change without notice.
Please refer to www.littelfuse.com for current information.
Broadband Optimized™ Protection
SDP Biased Series
Description
Features & Benefits
t$PNQBUJCMFXJUI7%4-
(30MHz)
t#BMBODFEPWFSWPMUBHF
protection
t-PXEJTUPSUJPO
t-PXJOTFSUJPOMPTT
t-PXQSPmMF
t40GPPUQSJOUDPNQBUJCMF
t'BJMTTIPSUDJSDVJUXIFO
surged in excess of ratings
Applicable Global Standards
Electrical Characteristics
Part Number Marking
V
DRM
@I
DRM
=5μA V
S
@100V/μs I
H
I
S
I
T
V
T
@I
T
=2.2
Amps
Capacitance
V min V max mA min mA max A max V max
SDP0080Q38CB SDP-8C 6 25 50 800 2.2 8
See Capacitance vs
Voltage Chart
SDP0640Q38CB SDP06C 58 77 150 800 2.2 8
SDP0720Q38CB SDP07C 65 88 150 800 2.2 8
SDP0900Q38CB SDP09C 75 98 150 800 2.2 8
SDP1100Q38CB SDP11C 90 130 150 800 2.2 8
SDP1300Q38CB SDP13C 120 160 150 800 2.2 8
SDP1800Q38CB SDP18C 170 220 150 800 2.2 8
SDP2600Q38CB SDP26C 220 300 150 800 2.2 8
SDP3100Q38CB SDP31C 275 350 150 800 2.2 8
SDP3500Q38CB SDP35C 320 400 150 800 2.2 8
Notes:
- Absolute maximum ratings measured at T
A
= 25ºC (unless otherwise noted).
- Devices are bi-directional (unless otherwise noted).
t5*""
t*56,&OIBODFE
Level
t*56,#BTJD-FWFM
t*&$
t(3*OUFSCVJMEJOH
t(3*OUSBCVJMEJOH
t:%5
t:%5
t:%5
Pinout Designation
Agency Approvals
Agency Agency File Number
E133083
Schematic Symbol
1
2
3
4
8
7
6
5
Tip in
Tip out
- Bias
+ Bias
Ground
Ground
Ring in Ring out
SDP Biased Series - 5x6 QFN
This new SDP Biased series provides overvoltage
protection for applications such as VDSL2, ADSL2, and
"%4-XJUINJOJNBMFGGFDUPOEBUBTJHOBMT5IJTMBUFTU
silicon design innovation results in a capacitive loading
characteristic that is compatible with these high bandwidth
applications. This surface mount QFN package provides a
surge capability that exceeds most worldwide standards
and recommendations for lightning surge withstand
capability of secondary protectors.
Line In (1)
Line In (4)
-Bias (2)
Ground (3)
(8) Line Out
(5) Line Out
(7) +Bias
(6) Ground
Phillip Havens Oct 2008
31
SIDACtor
®
Protection Thyristors
© 2009 Littelfuse, Inc.
Specifications are subject to change without notice.
Please refer to www.littelfuse.com for current information.
Broadband Optimized™ Protection
SDP Biased Series
Series
I
PP
I
TSM
2x10μs 1.2x50μs/8x20μs 10x700/5x310μs 10x1000μs
600V
RMS
1 cycle
A min A min A min A min
A
RMS
C 500 400 200 100 30
Surge Ratings
Parameter Name Test Conditions Value Units
I
TSM
Maximum non-reptitive
on-state current, 50/60Hz
0.5s 6.5
A
1s 4.6
2s 3.4
5s 2.3
30s 1.3
900s 0.73
50/60Hz Ratings
I
H
I
T
I
S
I
DRM
V
DRM
V
T
+
V
-V
+I
-I
V
S
V-I: Characteristics Capacitance vs. Voltage*
0
5
10
15
20
25
30
35
40
0010111.0
Line Voltage (V)
Capacitance (pF)
0V 3.3V
5V 12V
24V 30V
50V
Bias Voltage
* Bias voltage must be lower than V
DRM
Notes:
- Peak pulse current rating (I
PP
) is repetitive and guaranteed for the life of the product.
- I
PP
SBUJOHTBQQMJDBCMFPWFSUFNQFSBUVSFSBOHFPG$UP$
- The device must initially be in thermal equilibrium with -40°C < T
J
<¡$
Package Symbol Parameter Value Unit
5x6 QFN
T
J
Junction Temperature UP °C
T
STG
Storage Temperature Range UP °C
R
0JA
Thermal Resistance: Junction to Ambient 100 °C/W
Thermal Considerations
32
SIDACtor
®
Protection Thyristors
© 2009 Littelfuse, Inc.
Specifications are subject to change without notice.
Please refer to www.littelfuse.com for current information.
Broadband Optimized™ Protection
SDP Biased Series
-8
-40 -20 0 20 40 60 80 100 120 140 160
-6
-4
0
2
4
6
8
10
12
14
Junction Temperature (T
J
) – °C
Percent of V
S
Change – %
25 °C
25°C
Case Temperature (T
C
) - ºC
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
-40 -20 0 20 40 60 80 100 120 140 160
Ratio of
I
H
I
H
(T
C
= 25ºC)
Normalized V
S
Change vs. Junction Temperature
Normalized DC Holding Current vs. Case Temperature
Soldering Parameters
Physical Specifications
Environmental Specifications
Lead Material Copper Alloy
Terminal Finish 100% Matte-Tin Plated
Body Material
UL recognized epoxy meeting flammability
classification 94V-0
High Temp Voltage
Blocking
80% Rated V
DRM
(V
AC
Peak
¡$PS¡$
504 or 1008 hrs. MIL-STD-750 (Method 1040)
JEDEC, JESD22-A-101
Temp Cycling
¡$UP¡$NJOEXFMMVQUP
cycles. MIL-STD-750 (Method 1051) EIA/JEDEC,
JESD22-A104
Biased Temp &
Humidity
52 V
DC
¡$3)VQUPIST&*"
JEDEC, JESD22-A-101
High Temp Storage
¡$IST.*-45%.FUIPE
JEDEC, JESD22-A-101
Low Temp Storage -65°C, 1008 hrs.
Thermal Shock
¡$UP¡$NJOEXFMMTFDUSBOTGFS
10 cycles. MIL-STD-750 (Method 1056) JEDEC,
JESD22-A-106
Resistance to Solder
Heat
¡$TFDT.*-45%.FUIPE
Moisture Sensitivity
Level
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¡$1FBL+&%&$+45%-FWFM
Reflow Condition
Pb-Free assembly
(see Fig. 1)
Pre Heat
- Temperature Min (T
s(min)
)
¡$
- Temperature Max (T
s(max)
)
¡$
- Time (Min to Max) (t
s
)
60-180 secs.
Average ramp up rate (Liquidus Temp (T
L
)
to peak)
3°C/sec. Max.
T
S(max)
to T
L
- Ramp-up Rate
3°C/sec. Max.
Reflow
- Temperature (T
L
) (Liquidus)
¡$
- Temperature (t
L
)
60-150 secs.
Peak Temp (T
P
) ¡$
Time within 5°C of actual Peak Temp (t
p
)
30 secs. Max.
Ramp-down Rate 6°C/sec. Max.
Time 25°C to Peak Temp (T
P
)
8 min. Max.
Do not exceed ¡$
Time
Temperature
T
P
T
L
T
S(max)
T
S(min)
25
t
P
t
L
t
S
time to peak temperature
(t 25ºC to peak)
Ramp-down
Ramp-up
Preheat
Critical Zone
T
L
to T
P
Figure 1
Time
Temperature
T
P
T
L
T
S(max)
T
S(min)
25
t
P
t
L
t
S
time to peak temperature
(t 25ºC to peak)
Ramp-down
Ramp-up
Preheat
Critical Zone
T
L
to T
P
Figure 1
P1-P3P4-P5

SDP1300Q38CB

Mfr. #:
Buy SDP1300Q38CB
Manufacturer:
Littelfuse
Description:
Thyristor Surge Protection Devices (TSPD) SDP Biased xDSL 100A Protection Device
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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