P5P2304AF-2-08SR

ASM5P2304A
3.3 V
Zero Delay
Buf
fer
Description
ASM5P2304A is a versatile, 3.3 V zero−delay buffer designed to
distribute high−speed clocks in PC, workstation, datacom, telecom
and other high−performance applications. It is available in 8−pin
package. The part has an on−chip PLL which locks to an input clock
presented on the REF. The PLL feedback is required to be driven to
FBK pin, and can be obtained from one of the outputs. The
input−to−output propagation delay is guaranteed to be less than
±250 pS, and the output−to−output skew is guaranteed to be less than
200 pS.
ASM5P2304A has two banks of two outputs each. Multiple
ASM5P2304A devices can accept the same input clock and distribute
it. In this case the skew between the outputs of the two devices is
guaranteed to be less than 500 pS.
ASM5P2304A is available in two different configurations. Refer
to
ASM5P2304A
Configurations
Table. The ASM5P2304A−1 is the base
part, where the output frequencies equal the reference if there is no
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SOIC
8
S
SUFFIX
CASE 751BD
PIN CONFIGURA
TION
1
counter in the feedback path. The ASM5P2304A−1H is the high−drive
version of the −1 and the rise and fall times on this device are faster.
ASM5P2304A−2 allows the user to obtain REF and 1/2x or 2x
frequencies on each output bank. The exact configuration and output
frequencies depend on which output drives the feedback pin.
Features
REF
CLKA1
CLKA2
GND
(Top View)
FBK
V
DD
CLKB2
CLKB1
Zero Input−Output Propagation Delay, Adjustable by Capacitive
Load on FBK
Input
Multiple Configurations
Refer to ASM5P2304A Configurations Table
Input Frequency Range: 10 MHz to 133 MHz
Multiple Low−skew Outputs
Output−Output Skew less than 200 pS
Device−Device Skew less than 500 pS
Two Banks of Two Outputs Each
Less than 200 pS Cycle−to−Cycle Jitter
(−1, −1H, −2, 2H)
8−pin SOIC Package
3.3 V Operation
Commercial and Industrial Temperature Range
Advanced 0.35 !! CMOS Technology
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
August, 2011 Rev. 3
1 Publication Order Number:
ASM5P2304A/D
ASM5P2304A
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2
REFInput to CLKA / CLKB Delay (pS)
FBK
REF
PLL
CLKA1
CLKA2
/2 Extra Divider (2)
CLKB1
CLKB2
Figure 1. Block Diagram
Table 1. ASM5P2304A CONFIGURATIONS
Device Feedback From Bank A Frequency Bank B Frequency
ASM5P2304A (1, 1H)
Bank A or Bank B
Reference
Reference
ASM5P2304A (2, 2H)
Bank
A
Reference Reference /2
ASM5P2304A (2, 2H)
Bank
B
2 x Reference Reference
Zero Delay and Skew Control
For applications requiring zero input−output delay, all outputs must be equally loaded.
1500
1000
500
0
500
1000
30 25
20
15
10 5 0
5
10 15
20 25 30
1500
Output Load Difference: FBK Load CLKA/CLKB Load (pF)
Figure 2. REF Input to CLKA/CLKB Delay vs. Difference in
Loading
between FBK Pin and CLKA/CLKB
Pins
To close the feedback loop of the ASM5P2304A, the FBK
pin can be driven from any of the four available clock
outputs. The output driving the FBK pin will be driving a
total load of 7 pF plus any additional load that it drives. The
relative loading of this output (with respect to the remaining
outputs) can adjust the input−output delay. This is shown in
the above graph.
For applications requiring zero input−output delay, all
outputs including the one providing feedback should be
equally loaded. If input−output delay adjustments are
required, use the above graph to calculate loading
differences between the feedback output and remaining
outputs. For zero output−output skew, be sure to load outputs
equally.
ASM5P2304A
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3
Table 2. PIN DESCRIPTION
Pin # Pin Name
Description
1
Input reference clock frequency, 5 V tolerant input
2 CLKA1 (Note 2) Buffered clock output, bank A
3 CLKA2 (Note 2) Buffered clock output, bank A
4 GND Ground
5 CLKB1 (Note 2) Buffered clock output, bank B
6 CLKB2 (Note 2) Buffered clock output, bank B
7
V
DD
3.3 V supply
8
FBK
PLL feedback input
1. Weak pulldown.
2. Weak pulldown on all outputs.
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max Unit
Supply Voltage to Ground Potential
0.5
+4.6
V
DC Input Voltage (Except REF)
0.5
V
DD
+ 0.5
V
DC Input Voltage (REF)
0.5
7
V
Storage Temperature
65
+150 °C
Max. Soldering Temperature (10 sec)
260 °C
Junction Temperature
150
°C
Static Discharge Voltage (As per JEDEC STD22 A114B)
2000
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

P5P2304AF-2-08SR

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 10-133MHZ 3.3V 4 O/P ZDB
Lifecycle:
New from this manufacturer.
Delivery:
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