Table 6. SWITCHING CHARACTERISTICS (Notes 5, 6)
Parameter Test
Conditions
Min Typ Max Unit
(−2, −2H) devices 12
100
15 pF load
(−1, −1H) devices 10
133
Duty Cycle (Note 7)
(−1, −2, −1H, −2H)
Measured at 1.4 V,
F
OUT
< 66.66 MHz, 30 pF load
40 50 60 %
Duty Cycle (Note 7)
(−1, −2,−1H, −2H)
Measured at 1.4 V,
F
OUT
≤ 50 MHz, 15 pF load
45 50 55 %
Output Rise Time (Note 7)
(−1, −2)
Measured between 0.8 V
and 2.0 V, 30 pF load
Commercial temp.
2.2
nS
Industrial temp.
2.5
Output Rise Time (Note 7)
(−1H, −2H)
and 2.0 V, 30 pF load
Commercial temp.,
Industrial temp.
Output Rise Time (Note 7)
(−1, −2)
and 2.0 V, 15 pF load
Output Fall Time (Note 7)
(−1, −2)
and 0.8 V, 30 pF load
Industrial temp.
2.5
Output Fall Time (Note 7)
(−1H, −2H)
Measured between 2.0 V
and 0.8 V, 30 pF load
Commercial temp.,
Industrial temp.
1.25 1.5 nS
Output Fall Time (Note 7)
(−1, −2)
Measured between 2.0 V
and 0.8 V, 15 pF load
1.5 nS
Output−to−output skew on same bank
(−1, −1H, −2, −2H) (Note 7)
All outputs equally loaded
200
pS
Output bank A −to− output bank B
skew (−1, −1H)
All outputs equally loaded
200
Output bank A to output Bank B
skew (−2, −2H) (Note 7)
All outputs equally loaded
400
Delay, REF Rising Edge to FBK
Rising Edge (Note 7)
Measured at V
DD
/2
0 ±250 pS
Device−to−Device Skew (Note 7)
Measured at V
DD
/2 on the FBK pins of the device
0 500 pS
(Note 7)
Measured at 66.67 MHz, loaded outputs, 15 pF load
Measured at 66.67 MHz, loaded outputs, 30 pF load
200
Measured at 133 MHz, loaded outputs, 15 pF load
125
Measured at 66.67 MHz, loaded outputs, 15 pF load
Measured at 66.67 MHz, loaded outputs, 30 pF load
400
PLL Lock Time (Note 7) Stable power supply, valid clock presented on
REF and FBK pins
1.0 mS
5. For all measurements use Test Circuit #1.
6. All parameters are specified at Commercial and Industrial temperature unless stated otherwise.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
