16/19
BDxxIA5WEFJ
Datasheet
TSZ02201-0R6R0A600440-1-2
© 2012 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ2211115001
21.Dec.2012 Rev.002
Operational Notes
(1) Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the device, thus making it impossible to identify the damage mode, such as a short circuit or an open circuit.
If there is any possibility of exposure over the rated values, please consider adding circuit protection devices such as
fuses.
(2) Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage the IC. Take precautions when connecting the power
supply lines. An external direction diode can be added.
(3) Power supply lines
Design the PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply
line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply
terminals to ICs, connect a capacitor between the power supply and GND terminal. When using electrolytic capacitors in
a circuit, note that capacitance values are reduced at low temperatures and over time.
(4) GND voltage
The potential of the GND pin must be minimum potential under all operating conditions.
(5) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
(6) Off-leakage at high temperature.
Off-leakage at high temperature may increase because of manufacturing variations.
Design should consider the typical & worst cases shown below.
(7) Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
(8) Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
(9) ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.
(10) Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is
designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation.
Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit
is assumed.
TSD ON Temperature[] (typ.) Hysteresis Temperature [] (typ.)
BdxxIA5WEFJ 175 15
Ta-Ileak
0
0.1
0.2
0.3
0.4
0.5
25 50 75 100 125 150
Temperature ()
Ileak (mA)
typ
worst
17/19
BDxxIA5WEFJ
Datasheet
TSZ02201-0R6R0A600440-1-2
© 2012 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ2211115001
21.Dec.2012 Rev.002
(11) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC’s power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
(12) Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic
diode or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
(13) Ground Wiring Pattern.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change
the GND wiring pattern of any external components, either.
Resistor Transistor (NPN)
N
N N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin A
N
N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin B
C
B
E
N
GND
Pin A
P
aras
iti
c
element
Pin B
Other adjacent elements
E
B C
GND
P
aras
iti
c
element
18/19
BDxxIA5WEFJ
Datasheet
TSZ02201-0R6R0A600440-1-2
© 2012 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ2211115001
21.Dec.2012 Rev.002
Physical Dimension Tape and Reel Information
Marking Diagram
xx Product Name
00 BD00IA5WEFJ
10 BD10IA5WEFJ
12 BD12IA5WEFJ
15 BD15IA5WEFJ
18 BD18IA5WEFJ
25 BD25IA5WEFJ
30 BD30IA5WEFJ
33 BD33IA5WEFJ
(Unit : mm)
HTSOP-J8
0.08 S
0.08
M
S
1.0MAX
0.85±0.05
1.27
0.08±0.08
0.42
+0.05
-
0.04
1.05±0.2
0.65±0.15
4
°
+
6
°
4
°
0.17
+0.05
-
0.03
234
568
(MAX 5.25 include BURR)
7
1
0.545
(3.2)
4.9±0.1
6.0±0.2
(2.4)
3.9±0.1
1PIN MARK
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
2500pcs
E2
()
Direction of feed
Reel
1pin
HTSOP-J8(TOP VIEW)
xxIA5W
Part Number Marking
LOT Number
1PIN MARK

BD15IA5WEFJ-E2

Mfr. #:
Manufacturer:
Description:
LDO Voltage Controllers LDO Reg Pos 1.5V 0.5A
Lifecycle:
New from this manufacturer.
Delivery:
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