AD7747
Rev. 0 | Page 23 of 28
CAPDIFF = 1
±8pF
CDC
CAPDAC(+)
17pF
CAPDAC(–)
17pF
05469-021
C
Y
17pF
SHLD
CIN(+)
CIN(–)
0x000000
TO
0xFFFFFF
DATA
C
X
9 TO 25pF
(17pF ± 8pF)
Figure 32. Using CAPDAC in Differential Configuration
PARASITIC CAPACITANCE
The CDC architecture used in the AD7747 measures the
capacitance C
X
connected between the CIN pin and ground.
Most applications use the active shield to avoid external influ-
ences during the CDC. However, any parasitic capacitance, C
P
,
as shown in
Figure 33, can affect the CDC result.
DATA
CDC
SHLD
CIN
C
X
C
P1
C
P2
C
P3
05469-041
Figure 33. Parasitic Capacitance
A parasitic capacitance, C
P1
, coupled in between CIN and
ground adds directly to the value of the capacitance C
X
and,
therefore, the CDC result is: DATA ≈ C
X
+ C
P1
. An offset cali-
bration might be sufficient to compensate for a small parasitic
capacitance (C
P1
≤ 1pF). For a larger parasitic capacitance, the
CAPDAC can be used to compensate, followed by an offset
calibration to ensure the full range of ±8pF is available for
the system.
Other parasitic capacitances, such as C
P2
between active shield
and ground as well as C
P3
between the CIN pin and SHLD,
could influence the conversion result. However, the graphs in
the
Typical Performance Characteristics section show that the
effect of parasitic capacitance of type C
P2
/C
P3
below 250 pF is
insignificant to the CDC result.
Figure 7 and Figure 8 show the
gain error caused by C
P2
. Figure 9 shows the gain error caused
by C
P3
.
PARASITIC RESISTANCE
DATA
CDC
SHLD
CIN
C
X
R
P1
R
P3
R
P2
05649-042
Figure 34. Parasitic Resistance on CIN
Parasitic resistances, as shown in Figure 34, cause leakage
currents, which affect the CDC result. The AD7747 CDC
measures the charge transfer between the CIN pin and ground.
Any resistance connected in parallel to the measured
capacitance, C
X
, such as the parasitic resistance, R
P1
, also
transfers charge. Therefore, the parallel resistor is seen as an
additional capacitance in the output data. A resistance in the
range of R
P1
≥ 10 M causes an offset error in the CDC result.
An offset calibration can be used to compensate for the effect of
small leakage currents. A higher leakage current to ground,
R
P1
≤ 10 M, results in a gain error, an offset error, and a
nonlinearity error. See
Figure 10 in the Typical Performance
Characteristics section.
A parasitic resistance, R
P2
, between SHLD and ground, as well
as R
P3
between the CIN pin and the active shield, as shown in
Figure 34, cause a leakage current, which affects the CDC result
and is seen as an offset in the data. An offset calibration can be
used to compensate for effect of the small leakage current
caused by a resistance R
P2
and R
P3
≥ 200 k. See Figure 11,
Figure 12, and Figure 13 in the Typical Performance
Characteristics section.
PARASITIC SERIAL RESISTANCE
DATA
CDC
SHLD
CIN
C
X
R
S
5469-043
Figure 35. Parasitic Serial Resistance
The AD7747 CDC result is affected by a resistance in series
with the measured capacitance. The serial resistance should be
less than 10 kΩ for the specified performance. See
Figure 14 in
the
Typical Performance Characteristics section.
CAPACITIVE GAIN CALIBRATION
The AD7747 gain is factory calibrated for the full scale of
±8.192 pF in the production for each part individually. The
factory gain coefficient is stored in a one-time programmable
(OTP) memory and is copied to the capacitive gain register at
power-up or after reset.
The gain can be changed by executing a capacitance gain calibra-
tion mode, for which an external full-scale capacitance needs
to be connected to the capacitance input, or by writing a user
value to the capacitive gain register. This change would be only
temporary, and the factory gain coefficient would be reloaded
back after power-up or reset. The part is tested and specified for
use only with the default factory calibration coefficient.
