MC14532B
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7
Figure 4. Two MC14532B’s Cascaded for 4–Bit Output
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Q1 Q0Q2 Q1 Q0Q2
Q1 Q0Q2Q3
GS
3/4 MC14071B
V
DD
E
in
E
out
E
in
E
out
E
out
= 1"
WITH D
in
= 0"
Figure 5. Digital to Analog and Analog to Digital Converter
DIGITAL TO ANALOG CONVERSION
The digital eight–bit word to be converted is applied to the
inputs of the MC14512 with the most significant bit at
X7 and the least significant bit at X0. A clock input of up to
2.5 MHz (at V
DD
= 10 V) is applied to the MC14520B.
A compromise between I
bias
for the MC1710 and ∆R
between N and P–channel outputs gives a value of R of
33 k ohms. In order to filter out the switching frequencies,
RC should be about 1.0 ms (if R = 33 k ohms, C 0.03 µF).
The analog 3.0 dB bandwidth would then be dc to 1.0 kHz.
ANALOG TO DIGITAL CONVERSION
An analog signal is applied to the analog input of the
MC1710. A digital eight–bit word known to represent a dig-
itized level less than the analog input is applied to the
MC14512 as in the D to A conversion. The word is increm-
ented at rates sufficient to allow steady state to be reached
between incrementations (i.e. 3.0 ms). The output of the
MC1710 will change when the digital input represents the
first digitized level above the analog input. This word is the
digital representation of the analog word.
ANALOG
OUTPUT
CLOCK
INPUT
ANALOG
INPUT
V
DD
X7 X6 X5 X4 X3 X2 X1 X0
MC14512
A
B
C
MC1710
R
C
Z
V
DD
V
SS
E
in
D0 D1 D2 D3 D4 D5 D6 D7
Q2 Q0Q1
STOP
WORD
INCREMENTATION
Q2 Q4Q3Q1 Q2 Q4Q3Q1
CE RCE R
1/2 MC14520B 1/2 MC14520B
DIGITAL INPUT/OUTPUT
8-BIT WORD
TO BE CONVERTED
