PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 6 of 28
NXP Semiconductors
PCA9543A/43B
2-channel I
2
C-bus switch with interrupt logic and reset
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9543A/43B, which will be stored in the control register. If multiple bytes
are received by the PCA9543A/43B, it will save the last byte received. This register can
be written and read via the I
2
C-bus.
6.2.1 Control register definition
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the
control register. This register is written after the PCA9543A/43B has been addressed. The
2 LSBs of the control byte are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a STOP condition has been
placed on the I
2
C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when
the channel is made active, so that no false conditions are generated at the time of
connection.
Bits INT0, INT1, D6 and D7 are all writable, but will read the chip status. INT0 and INT1
indicate the state of the corresponding interrupt input. D7 and D6 always read 0.
See Section 6.2.2
.
Table 5. PCA9543B address map
Pin connectivity Address of PCA9543B Address byte value 7-bit
hexadecimal
address
without R/W
A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read
V
SS
V
SS
1111000 - F0h F1h 78h
V
SS
V
DD
1111001 - F2h F3h 79h
V
DD
V
SS
1111010 - F4h F5h 7Ah
V
DD
V
DD
1111011 - F6h F7h 7Bh
Fig 6. Control register
002aab181
X X
INT
1
INT
0
X X B1 B0
channel selection bits
(read/write)
76543210
interrupt bits (read/write),
but reads back chip status;
bit 6 and bit 7 always read 0
channel 0
channel 1
INT0
INT1
