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PS8382C 11/06/08
Product Pin Configuration
Logic Block Diagram
PI6C2502
Product Description
The PI6C2502 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback FB_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero.
Product Features
• High-Performance Phase-Locked-Loop Clock Distribution
for Networking,
• Synchronous DRAM modules for server/workstation/
PC applications
• Allows Clock Input to have Spread Spectrum
modulation for EMI reduction
• Zero Input-to-Output delay
• Low jitter: Cycle-to-Cycle jitter ±100ps max.
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
• Operates at 3.3V V
CC
• Wide range of Clock Frequencies up to 80 MHz
• Package (Pb-Free & Green): Plastic 8-pin SOIC Package (W)
8-Pin
W
Phase-Locked Loop Clock Driver
Application
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends the use of a zero-delay buffer
and an eighteen output non-zero-delay buffer. As shown in Figure
1, this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Figure 1. This Combination Provides Zero-Delay Between the
Reference Clocks Signal and 17 Outputs
CLK_IN
FB_IN
PLL
AV
CC
FB_OUT
CLK_OUT
1
2
3
V
CC
4
CLK_OUT
CLK_IN
GND
FB_IN
8
7
6
5
AGND
FB_OUT
AV
CC
17
Zero Delay
Buffer
PI6C2502
Reference
Clock
Signal
CLK_OUT
Feedback
18 Output
Non-Zero
Delay
Buffer
V
