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L9825

P1-P3P4-P6P7-P9P10-P11
L9825
4/11
ELECTRICAL CHARACTERISTCS
(4.5V
≤
V
CC
≤
5.5V; -40°C
≤
T
J
≤
150°C; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Supply voltage
I
ccSTB
Standby current without load 5 mA
I
ccOPM
Operating mode I
OUT1 ... 8
= 500mA
SPI - CLK = 3MHz
NCS = LOW
SDO no load
5mA
ΔI
CC
ΔI
CC
during reverse output
current
I
out
= -3A 100 mA
Inputs (NONx. NCS, CLK, SDI, nRes)
V
INL
Low level -0.3
0.2·V
CC
V
V
INH
High level
0.7·V
CC
V
CC
+0.3
V
V
hyst
Hysteresis voltage 0.85 V
I
IN
Input current V
IN
= V
CC
10 µA
R
IN
Pullup resistance 50 250 kΩ
C
IN
Input capacitance 10 pF
Serial data outputs
V
SDOH
High output level I
SDO
= -4mA
V
CC
-0.4
V
V
SDOL
Low output level I
SDO
= 3,2mA 0.4 V
I
SDOL
Tristate leakage current NCS = high; 0V ≤ V
SDO
≤ V
CC
-10 10 µA
C
SDO
Output capacitance f
SDO
= 300kHz 10 pF
Outputs OUT 1 ... 8
I
OUTL1 - 8
Leakage current OUTx = OFF; V
OUTx
= 25V; V
CC
= 5V
100 µA
I
OUTL1 - 8
Leakage current OUTx = OFF; V
OUTx
= 16V; V
CC
= 5V
100 µA
I
OUTL1 - 8
Leakage current OUTx = OFF; V
OUTx
= 16V; V
CC
= 1V
10 µA
V
clp
Output clamp voltage 1mA ≤ I
clp
≤ I
outp
; I
test
= 10mA
with correlation
45 60 V
R
DSon
On resistance OUT 1 ... 8 I
OUT
= 500mA; T
j
= +150°C 1.5 W
C
OUT
Output capacitance V
OUT
= 16V; f = 1MHz 300 pF
Outputs short circuit protection
I
SBC
Overcurrent shutoff threshold OUT1 ... OUT6 1.05 1.4 2.05 A
I
LIM
Short circuit current limitation OUT7; OUT8 1.05 1.4 1.75 A
t
SCB
Delay shutdown for output 1 ... 6; I
OUT
≤ 1/2 I
SBC
0.2 3 12 µs
5/11
L9825
Diagnostics
V
DG
Diagnostic threshold voltage
0.32·V
CC
0.4·V
CC
V
I
OL
Open load detection sink current V
out
= V
DG
20 100 µA
t
df
Diagnostic detection filter time for
output 1 & 2 on each diagnostic
condition
15 50 µs
Outputs timing
t
don1
Turn ON delay of OUT 1 and 2 NON
1, 2
= 50% to V
OUT
= 0.9·V
bat
NCS = 50% to V
OUT
= 0.9·V
bat
5µs
t
don2
Turn ON delay of OUT 3 to 8 NCS = 50% to V
OUT
= 0.9·V
bat
10 µs
t
doff
Turn OFF delay of OUT 1 to 8 NCS = 50% to V
OUT
= 0.1·V
bat
NON
1, 2
= 50% to V
OUT
= 0.1·V
bat
10 µs
dUon1/dt
Turn ON voltage slew-rate For output 3 to 8; 90% to 30% of
V
bat
; R
L
= 500Ω; V
bat
= 16V
0.7 3.5 V/µs
dUon2/dt
Turn ON voltage slew-rate For output 1 and 2; 90% to 30%
of V
bat
; R
L
= 500Ω; V
bat
= 16V
210V/µs
dUoff1/dt
Turn OFF voltage slew-rate For output 1 to 8; 30% to 90% of
V
bat
; R
L
= 500Ω; V
bat
= 16V
210V/µs
dUoff2/dt
Turn OFF voltage slew-rate For output 1 to 8; 30% to 80% of
V
bat
; R
L
= 500Ω; V
bat
= 0.9 · V
clp
215V/µs
Serial diagnostic link (Load capacitor at SDO = 100pF)
f
clk
Clock frequency 50% duty cycle 3 MHz
t
clh
Minimum time CLK = HIGH 160 ns
t
cll
Minimum time CLK = LOW 160 ns
t
pcld
Propagation delay
CLK to data at SDO valid
4.9V ≤ V
CC
≤ 5.1V 100 ns
t
csdv
NCS = LOW to data at SDO
active
100 ns
t
sclch
CLK low before NCS low
Setup time CLK to NCS change H/L
100 ns
t
hclcl
CLK change L/H after NCS = low 100 ns
t
scld
SDI input setup time CLK change H/L after SDI data
valid
20 ns
t
hcld
SDI input hold time
SDI data hold after CLK change H/L
20 ns
t
sclcl
CLK low before NCS high 150 ns
t
hclch
CLK high after NCS high 150 ns
t
pchdz
NCS L/H to output data float 100 ns
NCS pulse filter time Multiple of 8 CLK cycles
ELECTRICAL CHARACTERISTCS
(continued)
(4.5V
≤
V
CC
≤
5.5V; -40°C
≤
T
J
≤
150°C; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
L9825
6/11
FUNCTIONAL DESCRIPTION
General
The L9825 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the device using
the Serial Peripheral Interface, SPI protocol. Outputs 1 and 2 can be controlled parallel or serial. The power
outputs features voltage clamping function for flyback current recirculation and are protected against short cir-
cuit to Vbat.
The diagnostics recognizes two outputs fault conditions: 1) overcurrent for outputs 1 to 6 , overcurrent and ther-
mal overload for outputs 7 and 8 in switch-on condition and 2) open load or short to GND in switch-off condition
for all outputs. The outputs status can be read out via the serial interface.
The chip internal reset is a OR function of the external nRes signal and internally generated undervoltage nRes
signal.
Output Stages Control
Each output is controlled with its latch and with common reset line, which enables all eight outputs. Outputs 1
and 2 can be controlled also by its NON1, NON2 inputs. It allows PWM control independently on the SPI. These
inputs features internal pull-up resistors to assure that the outputs are switched off, when the inputs are open.
The control data are transmitted via the SDI input, the timing of the serial interface is shown in Fig. 1.
The device is selected with low NCS signal and the input data are transferred into the 8 bit shift register at every
falling CLK edge. The rising edge of the NCS latches the new data from the shift register to the drivers.
Figure 1. Timing of the Serial Interface
The SPI register data are transferred to the output latch at rising NCS edge. The digital filter between NCS and
the output latch ensures that the data are transferred only after 8 CLK cycles or multiple of 8 CLK cycles since
the last NCS falling edge. The NCS changes only at low CLK.
Table 1. Outputs Control
Outputs 1, 2: Outputs 3 to 8:
NON1,2 1001
SPI-bit 1,2 0 0 1 1 SPI-bit 3...8 0 1
Output 1, 2 off on on on Output 3...8 off on
NCS
CLK
SDI
SDO
tsclch thclcl tclh tcll tsclcl thclch
tcsdv tpcld tpchdz
not defined D8 D1
tscld
thcld
D8 D7 D1
P1-P3P4-P6P7-P9P10-P11

L9825

Mfr. #:
Buy L9825
Manufacturer:
STMicroelectronics
Description:
Power Switch ICs - Power Distribution Octal Low Side
Lifecycle:
New from this manufacturer.
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