SPC5515SAMLU66 Datasheet SPC5517EBMLQ66, SPC5517SAMLU66, SPC5514EBMLQ66 | P16-P18

MPC5510 Family Product Brief, Rev. 2

Features

Freescale Semiconductor16

— 16 channels offering dual-action operation with output pulse width modulation (PWM),

capture/compare capability and modulus up and down counters

• Buffered updates

• Edge-aligned or center-aligned output pulse width modulation

— Programmable pulse period and duty cycle

— Supports 0% and 100% duty cycle

— Shared or independent time bases

• Programmable phase shift between channels

2.6.14 Analog to Digital Converter Module (ADC)

The ADC features the following:

• 12-bit resolution

• 0–5 V common mode conversion range

• Up to 40 single-ended input channels, expandable with external multiplexers

• Conversions speeds of up to 800K samples/second possible

• Conversion calibration supported through dedicated hardware MAC

• Internal conversion triggering from periodic interrupt timer (PIT) or timed I/O module (eMIOS)

• Six conversion command and result queues with up to four deep FIFOs supporting prioritized

conversions

• Complex queuing supported through I/O processor

• Optional conversion timestamp

• All unused analog pins available as general purpose input pins

• Selected unused analog pins available as general purpose input/output pins

2.6.15 Deserial Serial Peripheral Interface Module (DSPI)

The DSPI features the following:

• Up to four DSPI modules supported

• Full-duplex, synchronous transfers

• Master or slave operation

• Programmable master bit rates

• Programmable clock polarity and phase

• End-of-transmission interrupt flag

• Programmable transfer baud rate

• Programmable data frames from 4 to 16 bits

• Up to six chip select lines available, depending on package and pin multiplexing, allowing 64

external devices to be selected using external multiplexing from a single DSPI

Features

MPC5510 Family Product Brief, Rev. 2

Freescale Semiconductor 17

• Up to eight independently configurable transfer types can be configured for each DSPI using the

clock and transfer attributes registers

• Chip-select strobe available as alternate function on one of the chip-select pins for de-glitching

• FIFOs for buffering up to four transfers on both the transmit and receive side

• Queueing operation possible through use of the I/O processor or eDMA

• Supports serialization of eMIOS200 channels

• General-purpose I/O functionality on pins when not used for SPI

2.6.16 Serial Communication Interface Module (eSCI)

The eSCI on the MPC5510 features the following:

• Up to eight eSCI modules supported

• LIN state machine and UART operating modes

• LIN state machine compliant to LIN1.3, LIN2.0, and LIN2.1 specifications

• LIN master mode state machine

— Supports generation of LIN message header

— Detection and flagging of LIN errors

— Classic or extended checksum calculation

— Supports autonomous LIN frame handling when combined with eDMA

• UART operating mode

— Standard non-return-to-zero (NRZ) mark/space format

— Full-duplex operation

— Software selectable word length (8-bit or 9-bit words)

— 10/11- or 13/14-bit break character possible

— 13-bit programmable baud rate modulus counter

— Separately enabled transmitter and receiver

— Separate receiver and transmitter CPU interrupt requests

— Programmable transmitter output polarity

— Two receiver wakeup methods

— Interrupt-driven operation with eight flags

— Receiver framing error detection

— Hardware parity checking

— 1/16 bit time noise reduction

2.6.17 Controller Area Network Module (FlexCAN)

The enhanced FlexCAN module features the following:

• Up to six FlexCAN modules supported

— Full implementation of the CAN protocol specification, version 2.0B

MPC5510 Family Product Brief, Rev. 2

Features

Freescale Semiconductor18

— 64 mailboxes, each configurable as transmit or receive

– Mailboxes configurable while module remains synchronized to CAN bus

• Transmit features

— Supports configuration of multiple mailboxes to form message queues of scalable depth

— Arbitration scheme according to message ID, message buffer number, or local buffer priority

— Internal arbitration to guarantee no inner or outer priority inversion

— Transmit abort procedure and notification

• Receive features

— Individual programmable filters for each mailbox

— Eight mailboxes optionally configurable as a six-entry receive FIFO

— Eight programmable acceptance filters for receive FIFO

• Programmable clock source

— System clock

— Direct oscillator clock to avoid PLL jitter

• Listen-only mode capabilities

• Configurable to disable reception of modules own transmitted messages to reduce interrupt loading

2.6.18 Inter IC Communications Module (I

The I

C module features the following:

• One I

C module supported

• Two-wire bidirectional serial bus for on-board communications

• Compatibility with I

C bus standard

• Multimaster operation

• Software-programmable for one of 256 different serial clock frequencies

• Software-selectable acknowledge bit

• Interrupt-driven, byte-by-byte data transfer

• Arbitration-lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• Start and stop signal generation/detection

• Repeated START signal generation

• Acknowledge bit generation/detection

• Bus-busy detection

2.6.19 Dual-Channel FlexRay Controller

The dual-channel FlexRay controller features the following:

• Optionally supported module

• Full implementation of FlexRay Protocol Specification 2.1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

SPC5515SAMLU66

Mfr. #:

Buy SPC5515SAMLU66

Manufacturer:

NXP / Freescale

Description:

32-bit Microcontrollers - MCU 768KB FLASH 125C

Lifecycle:

New from this manufacturer.

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SPC5515SAMLU66

SPC5515SAMLU66

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