8
COMMERCIAL TEMPERATURE RANGE
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
TM
WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
IDT72V3653L10
(4)
IDT72V3653L15
IDT72V3663L10
(4)
IDT72V3663L15
IDT72V3673L10
(4)
IDT72V3673L15
Symbol Parameter Min. Max. Min. Max. Unit
f
S Clock Frequency, CLKA or CLKB — 100 — 66.7 MHz
t
CLK Clock Cycle Time, CLKA or CLKB 10 — 15 — ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 4.5 — 6 — ns
t
CLKL Pulse Duration, CLKA and CLKB LOW 4.5 — 6 — ns
t
DS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 3—4—ns
tENS1 Setup Time, CSA and W/RA before CLKA↑; CSB and W/RB before CLKB↑ 4 — 4.5 — ns
t
ENS2 Setup Time, ENA, and MBA before CLKA↑; ENB and MBB before CLKB↑ 3 — 4.5 — ns
t
RSTS Setup Time, RS1 or PRS LOW before CLKA↑ or CLKB↑
(1)
5—5—ns
tFSS Setup Time, FS0, FS1 and FS2 before RS1 HIGH 7.5 — 7.5 — ns
tBES Setup Time, BE/FWFT before RS1 HIGH 7.5 — 7.5 — ns
tSDS Setup Time, FS0/SD before CLKA↑ 3—4—ns
tSENS Setup Time, FS1/SEN before CLKA↑ 3—4—ns
tFWS Setup Time, FWFT before CLKA↑ 0—0—ns
tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 0.5 — 1 — ns
tRTMS Setup Time, RTM before RT1; RTM before RT2 5—5—ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and MBB 0.5 — 1 — ns
after CLKB↑
tRSTH Hold Time, RS1 or PRS LOW after CLKA↑ or CLKB↑
(1)
4—4—ns
tFSH Hold Time, FS0, FS1 and FS2 after RS1 HIGH 2 — 2 — ns
tBEH Hold Time, BE/FWFT after RS1 HIGH 2 — 2 — ns
tSDH Hold Time, FS0/SD after CLKA↑ 0.5 — 1 — ns
tSENH Hold Time, FS1/SEN HIGH after CLKA↑ 0.5 — 1 — ns
tSPH Hold Time, FS1/SEN HIGH after RS1 HIGH 2 — 2 — ns
tRTMH Hold Time, RTM after RT1; RTM after RT2 5—5—ns
tSKEW1
(2)
Skew Time between CLKA↑ and CLKB↑ for EF/OR and FF/IR 5 — 7.5 — ns
tSKEW2
(2,3)
Skew Time between CLKA↑ and CLKB↑ for AE and AF 12 — 12 — ns
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
4. For 10ns speed grade:
Vcc = 3.3V ± 0.15V; TA = 0° to +70°.
(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0
ο
C to +70
ο
C; JEDEC JESD8-A compliant)