MC74HCT74ADG

© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 12
1 Publication Order Number:
MC74HCT74A/D
MC74HCT74A
Dual D Flip-Flop with Set
and Reset with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT74A is identical in pinout to the LS74. This device
may be used as a level converter for interfacing TTL or NMOS outputs
to High Speed CMOS inputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q
outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
Features
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
In Compliance With the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 136 FETs or 34 Equivalent Gates
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
LOGIC DIAGRAM
RESET 1
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
SET 2
1
2
3
4
13
12
11
10
5
6
9
8
Q1
Q1
Q2
Q2
PIN 14 = V
CC
PIN 7 = GND
Design Criteria Value Units
Internal Gate Count† 34 ea.
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0
mW
Speed Power Product .0075 pJ
Equivalent to a two−input NAND gate.
http://onsemi.com
See detailed ordering and shipping information on page 3 o
f
this data sheet.
ORDERING INFORMATION
PIN ASSIGNMENT
SET 1
CLOCK 1
DATA 1
RESET 1
11
12
13
14
8
9
105
4
3
2
1
7
6
SET 2
CLOCK 2
DATA 2
RESET 2
V
CC
Q2
Q2
GND
Q1
Q1
FUNCTION TABLE
Inputs Outputs
Set Reset Clock Data Q Q
LH XX HL
HL XX LH
L L X X H* H*
HH H HL
HH L LH
H H L X No Change
H H H X No Change
H H X No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredict
-
able if Set and Reset go high simultaneously.
MARKING DIAGRAM
A = Assembly Location
WL = Wafer Lot
Y, YY = Year
WW = Work Week
G = Pb−Free Package
SOIC−14 NB
D SUFFIX
CASE 751A
HCT74AG
AWLYWW
1
14
MC74HCT74A
http://onsemi.com
2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air SOIC Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types –55 +125
_C
t
r
, t
f
Input Rise and Fall Time (Figure 1) 0 500 ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbo
l
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
–55 to
25_C
85_C 125_C
V
IH
Minimum High−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| 20 mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| 20 mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
V
in
= V
IH
or V
IL
|I
out
| 4.0 mA 4.5 3.98 3.84 3.7
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| 4.0 mA 4.5 0.26 0.33 0.4
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 5.5 ± 0.1 ± 1.0 ± 1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
5.5 2.0 20 80
mA
DI
CC
Additional Quiescent Supply
Current
V
in
= 2.4 V, Any One Input
V
in
= V
CC
or GND, Other Inputs
l
out
= 0 mA
5.5
−55_C 25_C to 125_C
mA
2.9 2.4
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance
circuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND (V
in
or V
out
) V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HCT74A
http://onsemi.com
3
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ± 10%, C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbo
l
Parameter
Guaranteed Limit
Unit
–55 to
25_C
85_C 125_C
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
30 24 20 MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
24 30 36 ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
24 30 36 ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
15 19 22 ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
Typical @ 25°C, V
CC
= 5.0 V
pF
32
1. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
TIMING REQUIREMENTS (V
CC
= 5.0 V ± 10%, C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbo
l
Parameter Fig.
Guaranteed Limit
Units
–55 to
25_C
85_C 125_C
Min Max Min Max Min Max
t
su
Minimum Setup Time, Data to Clock 3 15 19 22 ns
t
h
Minimum Hold Time, Clock to Data 3 3 3 3 ns
t
rec
Minimum Recovery Time, Set or Reset Inactive to Clock 2 6 8 9 ns
t
w
Minimum Pulse Width, Clock 1 15 19 22 ns
t
w
Minimum Pulse Width, Set or Reset 2 15 19 22 ns
t
r
, t
f
Maximum Input Rise and Fall Times 1 500 500 500 ns
ORDERING INFORMATION
Device Package Shipping
MC74HCT74ADG SOIC−14 NB
(Pb−Free)
55 Units / Rail
MC74HCT74ADR2G SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

MC74HCT74ADG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops 5V CMOS Dual D-Type w/Set Reset
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union