ISL36411
11
FN6965.2
June 21, 2016
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About Q:ACTIVE™ Technology
Intersil has long realized that to enable the complex server
clusters of next generation data centers, it is critical to manage
the signal integrity issues of electrical interconnects. To address
this, Intersil has developed its groundbreaking Q:ACTIVE™
product line. By integrating its analog ICs inside cabling
interconnects, Intersil is able to achieve unsurpassed
improvements in reach, power consumption, latency and cable
gauge size as well as increased airflow in tomorrow’s data
centers. This new technology transforms passive cabling into
intelligent “roadways” that yield lower operating expenses and
capital expenditures for the expanding data center.
Intersil Lane Extenders allow greater reach over existing cabling
while reducing the need for thicker cables. This significantly
reduces cable weight and clutter, increases airflow and improves
power consumption.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com
.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask
.
Reliability reports are also available from our website at www.intersil.com/support
.
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest Rev.
DATE REVISION CHANGE
June 21, 2016 FN6965.2 Updated page 1 description of part.
Added applications bullet “DisplayPort v1.3 active copper cable modules”.
Removed “High-speed active cable assemblies” application bullet.
Added Related Literature section on page 1.
Added Table 1 on page 2.
Added Note 6 on page 6 and referenced in specification tables.
Replaced Products section with the About Intersil section.
Updated POD L46.4x7 to the latest revision changes are as follows:
-3/15/13 Side view, changed pkg thickness from 0.70+/-0.05 to 0.75+/-0.05 Detail x, changed from 0.152
REF to 0.203 REF.
March 16, 2010 FN6965.1 page 5
Control pin characteristics:
VOL: delete typical “0”
Input current: max 200, typ 100
page 6
Output res jitter: 0.35
In Entries from Lane-to-Lane Skew all the way down, all the numbers should move to typ column
Added High-Speed pins to ESD Ratings as follows to Abs Max Ratings:
ESD Ratings
Human Body Model
High-Speed Pins 1.5kV
All Other Pins 2kV
Removed board footprint from page 10 due to information covered in outline drawing.
February 8, 2010 FN6965.0 Initial Release
