83026AMILFT Datasheet 83026AMILF, 83026AMILFT | P4-P6

83026I Datasheet

AC Electrical Characteristics

Table 4. AC Characteristics, V

= 3.3V ± 0.3V, T

= -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

All parameters measured at f

MAX

unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the output at V

/2.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V

/2.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using

the same type of inputs on each device, the outputs are measured at V

/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

MAX

Output Frequency 350 MHz

Propagation Delay, NOTE 1 ƒ  350MHz 1.7 2.1 2.5 ns

tsk(o) Output Skew; NOTE 2, 4 5 20 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 600 ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

125MHz, Integration Range

(12kHz – 20MHz)

0.092 ps

/ t

Output Rise/Fall Time 0.8V to 2V 150 300 450 ps

odc Output Duty Cycle 40 50 60 %

83026I Datasheet

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

Offset Frequency (Hz)

SSB Phase Noise dBc/Hz

Additive Phase Jitter @ 125MHz

12kHz to 20MHz = 0.092ps (typical)

83026I Datasheet

Parameter Measurement Information

3.3V Core/3.3V LVCMOS Output Load AC Test Circuit

Output Skew

Output Duty Cycle/Pulse Width/Period

Differential Input Level

Part-to-Part Skew

Output Rise/Fall Time

SCOPE

GND

1.65V±0.15V

-1.65V±0.15V

sk(o)

Q0, Q1

GND

CLK

nCLK

CMR

Cross Points

tsk(pp)

Part 1

Part 2

0.8V

Q0, Q1

P1-P3 P4-P6 P7-P9 P10-P12

83026AMILFT

Mfr. #:

Buy 83026AMILFT

Manufacturer:

IDT

Description:

Clock Drivers & Distribution 1:2 Differential to LVCMOS Fanout Buffer

Lifecycle:

New from this manufacturer.

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83026AMILFT

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