ACPL-P341-500E Datasheet ACPL-P341-500E, ACPL-P341-060E, ACPL-W341-060E | P16-P18

Selecting the Gate Resistor (Rg)

Step 1: Calculate Rg minimum from the I

peak speci cation. The IGBT and Rg in Figure 22 can be analyzed as a simple

RC circuit with a voltage supplied by ACPL-P341/W341.

Rg ≥

– V

OLPEAK

15 V + 5 V – 2.5 V

= 5.8   6 

The V

value of 2.5 V in the previous equation is the V

at the peak current of 3.0 A.

Step 1: Check the ACPL-P341/W341 power dissipation and increase Rg if necessary. The ACPL-P341/W341 total power

dissipation (P

) is equal to the sum of the emitter power (P

) and the output power (P

= P

+ P

= I

• V

• Duty Cycle

= P

O(BIAS)

+ P

O(SWITCHING)

= I

• (V

-V

) + E

(Rg;Cg) • f

Using I

(worst case) = 16 mA, Rg = 5 , Max Duty Cycle = 80%, Cg = 25 nF, f = 25 kHz and T

max = 85° C:

= 16 mA • 1.95 V • 0.8 = 25 mW

= 3 mA • 20 V + 4.5 J • 25 kHz

= 60 mW + 112.5 mW

= 172.5 mW < 700 mW (P

O(MAX)

@ 85° C)

The value of 3 mA for I

in the previous equation is the maximum I

over the entire operating temperature range.

Since P

is less than P

O(MAX)

, Rg = 6  is alright for the power dissipation.

Figure 25. Energy Dissipated in the ACPL-P341/W341 for each IGBT switching

cycle.

2.0E-05

2.5E-05

3.0E-05

1.0E-05

1.5E-05

0.0E+00

5.0E-06

- ENERGY PER SWITCHING CYCLE - J

0 2468 10

Rg - Gate Resistance - 7

= 30 V

= 20 V

= 15 V

LED Drive Circuit Considerations for High CMR Performance

Figure 26 shows the recommended drive circuit for the

ACPL-P341/W341 that gives optimum common-mode

rejection. The two current setting resistors balance the

common mode impedances at the LED’s anode and

cathode. Common-mode transients can be capacitive

coupled from the LED anode, through C

(or cathode

through C

) to the output-side ground causing current

to be shunted away from the LED (which is not wanted

when the LED should be on) or conversely cause current

to be injected into the LED (which is not wanted when the

LED should be o ).

Table 8 shows the directions of I

and I

depend on the

polarity of the common-mode transient. For transients

occurring when the LED is on, common-mode rejection

(CM

, since the output is at “high” state) depends on

LED current (I

). For conditions where I

is close to the

switching threshold (I

FLH

), CM

also depends on the

extent to which I

and I

balance each other. In other

words, any condition where a common-mode transient

causes a momentary decrease in I

(i.e. when dV

/dt > 0

and |I

| > |I

|, referring to Table 8) will cause a common-

mode failure for transients which are fast enough.

Likewise for a common-mode transient that occurs when

the LED is o (i.e. CM

, since the output is at “low” state),

if an imbalance between I

and I

results in a transient

equal to or greater than the switching threshold of the

optocoupler, the transient “signal” may cause the output

to spike above 1 V, which constitutes a CM

failure. The

balanced I

LED

-setting resistors help equalize the common

mode voltage change at the anode and cathode. The

shunt drive input circuit will also help to achieve high CM

performance by shunting the LED in the o state.

+5 V

CATHODE

ANODE

OUT

= 5.0 V:

= 205 7 ±1%

= 137 7 ±1%

≈ 1.5

Figure 26. Recommended high-CMR drive circuit for the ACPL-P341/W341

Table 8. Common Mode Pulse Polarity and LED current Transients

/dt I

Direction I

Direction

If |I

| < |I

is momentarily

If |I

| > |I

is momentarily

Positive (>0) Away from LED anode

through C

Away from LED cathode

through C

Increase Decrease

Negative(<0) Toward LED anode

through C

Toward LED cathode

through C

Decrease Increase

Dead Time and Propagation Delay Speci cations

The ACPL-P341/W341 includes a Propagation Delay Dif-

ference (PDD) speci cation intended to help designers

minimize “dead time” in their power inverter designs. Dead

time is the time period during which both the high and

low side power transistors (Q1 and Q2 in Figure 22) are o .

Any overlap in Q1 and Q2 conduction will result in large

currents  owing through the power devices between the

high and low voltage motor rails.

To minimize dead time in a given design, the turn on of

LED2 should be delayed (relative to the turn o of LED1)

so that under worst-case conditions, transistor Q1 has

just turned o when transistor Q2 turns on, as shown in

Figure 27. The amount of delay necessary to achieve this

condition is equal to the maximum value of the propa-

gation delay di erence speci cation, PDD

MAX

, which is

speci ed to be 100 ns over the operating temperature

range of 40° C to 105° C.

Delaying the LED signal by the maximum propagation

delay di erence ensures that the minimum dead time is

zero, but it does not tell a designer what the maximum

dead time will be. The maximum dead time is equivalent

to the di erence between the maximum and minimum

propagation delay di erence speci cations as shown in

Figure 28. The maximum dead time for the ACPL-P341/

W341 is 200 ns (= 100 ns - (-100 ns)) over an operating

temperature range of -40° C to 105° C.

Note that the propagation delays used to calculate PDD

and dead time are taken at equal temperatures and test

conditions since the optocouplers under consideration

are typically mounted in close proximity to each other and

are switching identical IGBTs.

Figure 27. Minimum LED skew for zero dead time Figure 28. Waveforms for dead time

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

ACPL-P341-500E

Mfr. #:

Buy ACPL-P341-500E

Manufacturer:

Broadcom / Avago

Description:

Logic Output Optocouplers Gate Drive Opto

Lifecycle:

New from this manufacturer.

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ACPL-P341-500E

ACPL-P341-500E

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