16
1615J–PLD–01/06
ATF1502ASV
14. Power-down Mode
The ATF1502ASV includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply cur-
rent is reduced to less than 3 mA. During power-down, all output data and internal logic states
are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs that were in a high-Z state at the onset will remain at high-Z. During power-down, all
input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
ensure that pins do not float to indeterminate levels, further reducing system power. The power-
down pin feature is enabled in the logic design file. Designs using the power-down pin may not
use the PD pin logic array input. However, all other PD pin macrocell resources may still be
used, including the buried feedback and foldback product term array inputs.
Notes: 1. For slow slew outputs, add t
SSO
.
2. Pin or product term.
Table 14-1. Power-down AC Characteristics
(1)(2)
Symbol Parameter
-15 -20
UnitsMin Max Min Max
t
IVDH
Valid I, I/O before PD High 15 20 ns
t
GVDH
Valid OE
(2)
before PD High 15 20 ns
t
CVDH
Valid Clock
(2)
before PD High 15 20 ns
t
DHIX
I, I/O Don’t Care after PD High 25 30 ns
t
DHGX
OE
(2)
Don’t Care after PD High 25 30 ns
t
DHCX
Clock
(2)
Don’t Care after PD High 25 30 ns
t
DLIV
PD Low to Valid I, I/O 1 1 µs
t
DLGV
PD Low to Valid OE
(2)
11µs
t
DLCV
PD Low to Valid Clock
(2)
11µs
t
DLOV
PD Low to Valid Output 1 1 µs
