X1228S14I Datasheet X1228S14, X1228S14-2.7, X1228S14-2.7A | P22-P24

FN8100.4

May 18, 2006

Acknowledge Polling

Disabling of the inputs during nonvolatile write cycles

can be used to take advantage of the typical 5mS write

cycle time. Once the stop condition is issued to indi-

cate the end of the master’s byte load operation, the

X1228 initiates the internal nonvolatile write cycle.

Acknowledge polling can begin immediately. To do

this, the master issues a start condition followed by the

Memory Array Slave Address Byte for a write or read

operation (AEh or AFh). If the X1228 is still busy with

the nonvolatile write cycle then no ACK will be

returned. When the X1228 has completed the write

operation, an ACK is returned and the host can pro-

ceed with the read or write operation. Refer to the flow

chart in Figure 15. Note: Do not use the CCR Salve

byte (DEh or DFh) for Acknowledge Polling.

Read Operations

There are three basic read operations: Current

Address Read, Random Read, and Sequential Read.

Current Address Read

Internally the X1228 contains an address counter that

maintains the address of the last word read incre-

mented by one. Therefore, if the last read was to

address n, the next read operation would access data

from address n+1. On power-up, the sixteen bit

address is initialized to 0h. In this way, a current

address read immediately after the power-on reset

can download the entire contents of memory starting

at the first location.Upon receipt of the Slave Address

Byte with the R/W

bit set to one, the X1228 issues an

acknowledge, then transmits eight data bits. The mas-

ter terminates the read operation by not responding

with an acknowledge during the ninth clock and issu-

ing a stop condition. Refer to Figure 14 for the

address, acknowledge, and data transfer sequence.

Figure 15. Acknowledge Polling Sequence

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read

operation, the master must either issue a stop condi-

tion during the ninth cycle or hold SDA HIGH during

the ninth clock cycle and then issue a stop condition.

Figure 14. Current Address Read Sequence

ACK

returned?

Byte load completed

by issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

YES

Issue STOP

Continue normal

Read or Write

command

sequence

PROCEED

YES

nonvolatile write

Cycle complete. Continue

command sequence?

Issue Memory Array Slave

Address Byte

AFh (Read) or AEh (Write)

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

11111

X1228

FN8100.4

May 18, 2006

Random Read

Random read operations allows the master to access

any location in the X1228. Prior to issuing the Slave

Address Byte with the R/W

bit set to zero, the master

must first perform a “dummy” write operation.

The master issues the start condition and the slave

address byte, receives an acknowledge, then issues

the word address bytes. After acknowledging receipt

of each word address byte, the master immediately

issues another start condition and the slave address

byte with the R/W

bit set to one. This is followed by an

acknowledge from the device and then by the eight bit

data word. The master terminates the read operation

by not responding with an acknowledge and then issu-

ing a stop condition. Refer to Figure 16 for the

address, acknowledge, and data transfer sequence.

In a similar operation called “Set Current Address,” the

device sets the address if a stop is issued instead of

the second start shown in Figure 16. The X1228 then

goes into standby mode after the stop and all bus

activity will be ignored until a start is detected. This

operation loads the new address into the address

counter. The next Current Address Read operation will

read from the newly loaded address. This operation

could be useful if the master knows the next address it

needs to read, but is not ready for the data.

Sequential Read

Sequential reads can be initiated as either a current

address read or random address read. The first data

byte is transmitted as with the other modes; however,

the master now responds with an acknowledge, indi-

cating it requires additional data. The device continues

to output data for each acknowledge received. The

master terminates the read operation by not responding

with an acknowledge and then issuing a stop condition.

The data output is sequential, with the data from

address n followed by the data from address n + 1.

The address counter for read operations increments

through all page and column addresses, allowing the

entire memory contents to be serially read during one

operation. At the end of the address space the counter

“rolls over” to the start of the address space and the

X1228 continues to output data for each acknowledge

received. Refer to Figure 17 for the acknowledge and

data transfer sequence.

Figure 16. Random Address Read Sequence

Figure 17. Sequential Read Sequence

Slave

Address

Word

Address 1

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Word

Address 0

1111

0000000

Data

(2)

Slave

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(n-1)

(n is any integer greater than 1)

Data

(1)

X1228

FN8100.4

May 18, 2006

APPLICATION SECTION

CRYSTAL OSCILLATOR AND TEMPERATURE

COMPENSATION

Intersil has now integrated the oscillator compensation

circuity on-chip, to eliminate the need for external

components and adjust for crystal drift over tempera-

ture and enable very high accuracy time keeping

(<5ppm drift).

The Intersil RTC family uses an oscillator circuit with

on-chip crystal compensation network, including

adjustable load-capacitance. The only external com-

ponent required is the crystal. The compensation net-

work is optimized for operation with certain crystal

parameters which are common in many of the surface

mount or tuning-fork crystals available today. Table 6

summarizes these parameters.

Table 7 contains some crystal manufacturers and part

numbers that meet the requirements for the Intersil

RTC products.

The turnover temperature in Table 6 describes the

temperature where the apex of the of the drift vs. tem-

perature curve occurs. This curve is parabolic with the

drift increasing as (T-T0)

. For an Epson MC-405

device, for example, the turnover temperature is typi-

cally 25 deg C, and a peak drift of >110ppm occurs at

the temperature extremes of -40 and +85 deg C. It is

possible to address this variable drift by adjusting the

load capacitance of the crystal, which will result in pre-

dictable change to the crystal frequency. The Intersil

RTC family allows this adjustment over temperature

since the devices include on-chip load capacitor trim-

ming. This control is handled by the Analog Trimming

capacitance range covered by the ATR circuit is

approximately 3.25pF to 18.75pF, in 0.25pf incre-

ments. Note that actual capacitance would also

include about 2pF of package related capacitance. In-

circuit tests with commercially available crystals dem-

onstrate that this range of capacitance allows fre-

quency control from +116ppm to -37ppm, using a

12.5pF load crystal.

In addition to the analog compensation afforded by the

adjustable load capacitance, a digital compensation

feature is available for the Intersil RTC family. There

are three bits known as the Digital Trimming Register

or DTR, and they operate by adding or skipping pulses

in the clock signal. The range provided is ±30ppm in

increments of 10ppm. The default setting is 0ppm. The

DTR control can be used for coarse adjustments of

frequency drift over temperature or for crystal initial

accuracy correction.

Table 6. Crystal Parameters Required for Intersil RTC’s

Table 7. Crystal Manufacturers

Parameter Min Typ Max Units Notes

Frequency 32.768 kHz

Freq. Tolerance ±100 ppm Down to 20ppm if desired

Turnover Temperature 20 25 30 °C

Typically the value used for most

crystals

Operating Temperature Range -40 85 °C

Parallel Load Capacitance 12.5 pF

Equivalent Series Resistance 50 kΩ For best oscillator performance

Manufacturer Part Number Temp Range +25°C Freq Toler.

Citizen CM201, CM202, CM200S -40 to +85°C ±20ppm

Epson MC-405, MC-406 -40 to +85°C ±20ppm

Raltron RSM-200S-A or B -40 to +85°C ±20ppm

SaRonix 32S12A or B -40 to +85°C ±20ppm

Ecliptek ECPSM29T-32.768K -10 to +60°C ±20ppm

ECS ECX-306/ECX-306I -10 to +60°C ±20ppm

Fox FSM-327 -40 to +85°C ±20ppm

X1228

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

X1228S14I

Mfr. #:

Buy X1228S14I

Manufacturer:

Renesas / Intersil

Description:

IC RTC CLK/CALENDAR I2C 14-SOIC

Lifecycle:

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X1228S14I

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