74LVTH16952MEA

© 2001 Fairchild Semiconductor Corporation DS500103 www.fairchildsemi.com
January 2000
Revised October 2001
74LVT16952 • 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
74LVT16952 74LVTH16952
Low Voltage 16-Bit Registered Transceiver
with 3-STATE Outputs
General Description
The LVT16952 and LVTH16952 are 16-bit registered
transceivers. Two 8-bit back to back registers store data
flowing in both directions between two bidirectional buses.
Separate clock, clock enable, and output enable signals
are provided for each register.
The LVTH16952 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The registered transceiver is designed for low-voltage
(3.3V) V
CC
applications, but with the capability to provide a
TTL interface to a 5V environment.
The LVT16952 and LVTH16952 are fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining low power dissi-
pation.
Features
Input and output interface capability to systems at
5V V
CC
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16952)
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs source/sink
32 mA/+64 mA
Functionally compatible with the 74 series 16952
Latch-up conforms to JEDEC JED78
ESD performance:
Human-body model
> 2000V
Machine model
> 200V
Charged-device model
> 1000V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number Package Number Package Description
74LVT16952MEA
(Preliminary)
MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16952MTD
(Preliminary)
MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16952MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16952MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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74LVT16952 74LVTH16952
Connection Diagram Pin Descriptions
Truth Table
(Note 1)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = Output High Impedance
= LOW-to-HIGH Transition.
NC = No Change (state established by last valid CP)
B
0
= State established by last valid CP
Note 1: A to B data flow shown; B to A flow control is the same, but used
OEBA
n
, CPBA
n
and CEB
n
.
Pin Names Description
A
0
A
16
Data Register A Inputs
B-Register 3-STATE Outputs
B
0
B
16
Data Register B Inputs
A-Register 3-STATE Outputs
CPAB
n
, CPBA
n
Clock Pulse Inputs
CEA
n
, CEB
n
Clock Enable
OEAB
n
, OEBA
n
Output Enable Inputs
Inputs Internal Register Output
A
n
CPAB
n
CEA
n
OEAB
n
Value
B
n
XX H L NC B
0
XX H H NC Z
L
LL L L
L
LH L Z
H
LL H H
H
LH H Z
XL X L NC B
0
XH X L NC B
0
XL X H NC Z
XH X H NC Z
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74LVT16952 74LVTH16952
Logic Diagram
Note:
n
for either byte 1 or byte 2.
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

74LVTH16952MEA

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC TXRX NON-INVERT 3.6V 56SSOP
Lifecycle:
New from this manufacturer.
Delivery:
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