MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
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Note 1: For the MAX1319, V
IN
= 0 to +5V. For the MAX1323, V
IN
= -5V to +5V. For the MAX1327, V
IN
= -10V to +10V.
Note 2: INL is defined as the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: CONVST must remain low for at least the acquisition period.
Note 5: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
Note 6: Minimum clock frequency is limited only by the internal T/H droop rate. Limit the time between the falling edge of CONVST
to the falling edge of EOLC to a maximum of 0.25ms.
Note 7: To avoid T/H droop degrading the sampled analog input signals, the first clock pulse should occur within 10µs of the rising
edge of CONVST and have a minimum clock frequency of 100kHz.
TIMING CHARACTERISTICS (Figures 3, 4, 5, and 6) (Tables 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Internal clock 1.6 1.8 ns
Conversion Time t
CONV
External clock (Figure 4) 16
Clock
cycles
CONVST Pulse-Width Low
(Acquisition Time)
t
ACQ
(Note 4) 0.16 100 µs
CS Pulse Width t
2
30 ns
RD Pulse-Width Low t
3
30 ns
CS to RD Setup Time t
8
0ns
RD to CS Hold Time t
9
0ns
Data Access Time
(RD Low to Valid Data)
t
10
30 ns
Bus Relinquish Time (RD High) t
11
30 ns
Internal clock 80 ns
EOC Pulse Width t
12
External clock (Figure 4) 1
Clock
cycle
External CLK Period t
16
90 ns
External CLK High Period t
17
Logic sensitive to rising edges 20 ns
External CLK Low Period t
18
Logic sensitive to rising edges 20 ns
External Clock Frequency (Note 6) 0.1 12.5 MHz
Internal Clock Frequency 10 MHz
CONVST High to CLK Edge t
19
(Note 7) 20 ns
EOC Low to RD t
20
0ns
