MAX1327ECM+T Datasheet MAX1323ECM+, MAX1319ECM+, MAX1319ECM+T | P13-P15

MAX1319/MAX1323/MAX1327

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

______________________________________________________________________________________ 13

To start a conversion using external clock mode, pull

CONVST low for at least the acquisition time (t

ACQ

). The

T/H acquires the signal while CONVST is low, and con-

version begins on the rising edge of CONVST. Apply an

external clock to the CLK pin. To avoid T/H droop

degrading the sampled analog input signals, the first

clock pulse should occur within 10µs from the rising

edge of CONVST, and have a minimum clock frequency

of 100kHz. The conversion result is available for read on

the rising edge of the 17th clock cycle (Figure 4).

In both internal and external clock modes, CONVST

must be held high until the last conversion result is

read. For best operation, the rising edge of CONVST

must be a clean, high-speed, low-jitter digital signal.

It is necessary to have a period of inactivity on the digi-

tal bus during signal aquisition. t

QUIET

is the period

between the RD rising edge and the falling edge of

CONVST shown in Figure 4. Allow a minimum of 50ns

for t

QUIET

Reading a Conversion Result

Reading During a Conversion

Figures 3 and 4 show the interface signals for initiating

a read operation during a conversion cycle. CS can be

low at all times; it can be low during the RD cycles, or it

can be the same as RD.

After initiating a conversion by bringing CONVST high,

wait for EOC or EOLC to go low (about 1.6µs in internal

clock mode or 17 clock cycles in external clock mode)

before reading the first conversion result. Read the

conversion result by bringing RD low and latching the

data to the parallel digital-output bus. Bring RD high to

release the digital bus.

Power-Up Reset

After applying power, allow the 1.0ms wake-up time to

elapse before initiating the first conversion. If using an

external clock, apply 20 clock pulses to CLK with

CONVST high before initiating the first conversion. If

using an internal clock, hold CONVST high for at least

2.0µs after the wake-up time is complete.

Reference

Internal Reference

The internal reference circuits provide for analog input

voltages of 0 to +5V unipolar (MAX1319), ±5V bipolar

(MAX1323) or ±10V bipolar (MAX1327). Install external

capacitors for reference stability, as indicated in Table 1,

and as shown in the Typical Operating Circuits.

Figure 4. Reading a Conversion—External Clock

CONVST

CLK

TRACK

HOLD

D0–D13

SAMPLE

ACQ

QUIET

TRACK

EOC

1 2 3 16 17 18 19 20 1

MAX1319/MAX1323/MAX1327

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

14 ______________________________________________________________________________________

External Reference

Connect a +2.0V to +3.0V external reference at REF

and/or REF. When connecting an external reference,

the input impedance is typically 5kΩ. The external ref-

erence must be able to drive 200µA of current and be

less than 3Ω output impedance. For more information

about using external references see the Transfer

Functions section.

Layout, Grounding, and Bypassing

For best performance use PC boards. Board layout

should ensure that digital and analog signal lines are

separated from each other. Do not run analog and digi-

tal lines parallel to one another (especially clock lines),

or do not run digital lines underneath the ADC pack-

age. Figure 5 shows the recommended system ground

connections. A single-point analog ground (star ground

point) should be established at AGND, separate from

the logic ground. All other analog grounds and DGND

should be connected to this ground. No other digital

system ground should be connected to this single-point

analog ground. The ground return to the power supply

for this ground should be low impedance and as short

as possible for noise-free operation. High-frequency

noise in the V

power supply may affect the high-

speed comparator in the ADC. Bypass these supplies

to the single-point analog ground with 0.1µF and 2.2µF

bypass capacitors close to the device. If the +5V

power supply is very noisy, a ferrite bead can be con-

nected as a lowpass filter, as shown in Figure 5.

Transfer Functions

Bipolar ±10V Device

Table 2 and Figure 6 show the two’s complement trans-

fer function for the MAX1327 with a ±10V input range.

The full-scale input range (FSR) is eight times the volt-

age at REF. The internal +2.500V reference gives a

+20V FSR, while an external +2V to +3V reference

allows an FSR of +16V to +24V, respectively. Calculate

the LSB size using the following equation:

This equals 1.2207mV with a +2.5V internal reference.

The input range is centered about V

MSV

. Normally, MSV

= AGND, and the input is symmetrical at about zero. For

a custom midscale voltage, drive MSV with an external

voltage source. Noise present on MSV directly couples

into the ADC result. Use a precision, low-drift voltage ref-

erence with adequate bypassing to prevent MSV from

degrading ADC performance. For maximum full-scale

range, be careful not to violate the absolute maximum

voltage ratings of the analog inputs when choosing MSV.

Determine the input voltage as a function of V

REF

MSV

, and the output code in decimal using the follow-

ing equation:

Bipolar ±5V Device

Table 3 and Figure 7 show the two’s complement transfer

function for the MAX1323 with a ±5V input range. The

FSR is four times the voltage at REF. The internal +2.500V

reference gives a +10V FSR, while an external +2V to

+3V reference allows an FSR of +8V to +12V, respective-

ly. Calculate the LSB size using the following equation:

This equals 0.6104mV when using the internal reference.

The input range is centered about V

MSV

. Normally,

MSV = AGND, and the input is symmetrical at about

zero. For a custom midscale voltage, drive MSV with an

external voltage source. Noise present on MSV directly

couples into the ADC result. Use a precision, low-drift

voltage reference with adequate bypassing to prevent

MSV from degrading ADC performance. For maximum

full-scale range, be careful not to violate the absolute

LSB

REFADC

V LSB CODE V

CH MSV_

=× +

LSB

REFADC

Figure 5. Power-Supply Grounding and Bypassing

SUPPLIES

DD AGND DGND

DIGITAL

CIRCUITRY

OPTIONAL

FERRITE

BEAD

+5V RETURN RETURN+3V TO +5V

GND

MAX1319

MAX1323

MAX1327

maximum voltage ratings of the analog inputs when

choosing MSV. Determine the input voltage as a func-

tion of V

REF

, V

MSV

, and the output code in decimal

using the following equation:

V LSB CODE V

CH MSV_

=× +

MAX1319/MAX1323/MAX1327

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

______________________________________________________________________________________ 15

Figure 6. ±10V Bipolar Transfer Function

8 x V

REFADC

8 x V

REFADC

8 x V

REFADC

1 LSB =

TWO'S COMPLEMENT BINARY OUTPUT CODE

-8192 -8190 +8191+8189

0x2000

0x2001

0x2002

0x2003

0x1FFF

0x1FFE

0x1FFD

0x1FFC

0x3FFF

0x0000

0x0001

-1 0 +1

(MSV)

INPUT VOLTAGE (V

CH_

- V

MSV

IN LSBs)

Table 2. ±10V Bipolar Code Table

TWO’S COMPLEMENT

BINARY OUTPUT CODE

DECIMAL

EQUIVALENT

OUTPUT

(CODE

)

INPUT

VOLTAGE (V)

REF

= 2.5V,

MSV

= 0V)

01 1111 1111 1111 ➔

0x1FFF

8191 9.9988

01 1111 1111 1110 ➔

0x1FFE

8190 9.9976

00 0000 0000 0001 ➔

0x0001

1 0.0012

00 0000 0000 0000 ➔

0x0000

11 1111 1111 1111 ➔

0x3FFF

-1 -0.0012

10 0000 0000 0001 ➔

0x2001

-8191 -9.9988

10 0000 0000 0000 ➔

0x2000

-8192 -10.0000

Table 3. ±5V Bipolar Code Table

TWO’S COMPLEMENT

BINARY OUTPUT CODE

DECIMAL

EQUIVALENT

OUTPUT

(CODE

)

INPUT

VOLTAGE (V)

REF

= 2.5V,

MSV

= 0V)

01 1111 1111 1111 ➔

0x1FFF

8191 4.9994

01 1111 1111 1110 ➔

0x1FFE

8190 4.9988

00 0000 0000 0001 ➔

0x0001

1 0.0006

00 0000 0000 0000 ➔

0x0000

11 1111 1111 1111 ➔

0x3FFF

-1 -0.0006

10 0000 0000 0001 ➔

0x2001

-8191 -4.9994

10 0000 0000 0000 ➔

0x2000

-8192 -5.0000

Figure 7. ±5V Bipolar Transfer Function

4 x V

REFADC

4 x V

REFADC

4 x V

REFADC

1 LSB =

TWO'S COMPLEMENT BINARY OUTPUT CODE

-8192 -8190 +8191+8189

0x2000

0x2001

0x2002

0x2003

0x1FFF

0x1FFE

0x1FFD

0x1FFC

0x3FFF

0x0000

0x0001

-1 0 +1

(MSV)

INPUT VOLTAGE (V

CH_

- V

MSV

IN LSBs)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

MAX1327ECM+T

Mfr. #:

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IC ADC 14BIT 526KSPS 48LQFP

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MAX1327ECM+T

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