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S-8733A0EUP-APFT2G
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P45
P46-P48
P49-P51
P52-P53
HIGH WITHSTAND-VOLTAGE VOLTAGE
REGULATOR WITH RESET FUNCTION
Rev.8.0
_00
S-87x Series
Seiko Instrum
ents Inc.
25
Measurement Circuits
1.
C
L
VSS
VOUT
A
VIN
(SENSE)
)
VPF
(
V
2.
V
VSS
VOUT
VIN
VOR
100 k
Ω
(SENSE)
)
VPF
(
Figure 8
Figure 9
3.
VSS
VOUT
VIN
VOR
CD
100 k
Ω
C
D
4.
VSS
VOUT
VIN
VOR
A
V
(SENSE)
)
VPF
(
Figure 10
Figure 11
5.
VSS
VIN
A
(SENSE)
)
VPF
(
6.
VSS
VOUT
VIN
)
VPF
(
R
L
=
1 M
Ω
(SENSE)
V
Figure 12
Figure 13
7.
VSS
VIN
A
SENSE
Figure 14
HIGH WITHSTAND-VOLTAGE VOLTAGE
REGULATOR WITH RESET FUNCTION
S-87x Series
Rev.8.0
_00
Seiko Instrum
ents Inc.
26
Operation Timing Charts
1. Voltage regulator (C/G type)
*2
*1
H
L
PF
V [
V
]
t [s]
V
SS
V
OUT
[V]
t [s]
V
SS
V
IN
[V]
t
1
t [s]
V
SS
*1
t
2
*1.
Indicates shutdown state. When the
load current (I
OUT
) is less than 1
μ
A, the output voltage (V
OUT
) is
not always V
SS
level.
*2.
When the V
OUT
is shorted at t
1
, V
OUT
becomes V
SS
level. When the short of V
OUT
is removed at t
2
,
V
OUT
returns to normal output.
Figure 15
2. Voltage detector (A/B/F type)
+
V
DET
−
V
DET
t
pd
*1
t [s]
V
OR
[V]
V
IN
or V
OUT
[V]
t [s]
V
HYS
t
pd
*1
t
pd
*1
*1.
Output delay time (t
pd
) of the voltage detector can be changed
wi
th an external capacitance value to
CD pin. Delay circuit is not includ
ed in C/E/G type.
Remark
Pull up V
OR
through a resistor to V
IN
or V
OUT
.
Figure 16
HIGH WITHSTAND-VOLTAGE VOLTAGE
REGULATOR WITH RESET FUNCTION
Rev.8.0
_00
S-87x Series
Seiko Instrum
ents Inc.
27
3. When using the SENSE pin (E type)
V
OUT
[V]
t [s]
+
V
DET
−
V
DET
t [s]
t [s]
V
OR
[V]
V
IN
=
V
SENSE
*1
[V]
*1.
The SENSE pin is connected to VIN pin.
Remark
Pull up V
OR
through a resistor to V
OUT
.
Figure 17
Explanation of Terms
1. I/O voltage difference (V
dif
)
V
dif
=
V
IN1
−
V
OUT1
V
OUT1
:
Initial output voltage
V
IN1
:
Input voltage which generates an output voltage (V
OUT2
) decreased by 5 % from V
OUT1
2. Load regulation (
Δ
V
OUT2
)
Δ
V
OUT2
=
V
OUT1
−
V
OUT2
V
OUT1
:
Output voltage when I
OUT
is 50
μ
A
V
OUT2
:
Output voltage when I
OUT
is 40 mA
3. Line regulation (
Δ
V
OUT1
)
Δ
V
OUT1
=
V
OUT1
−
V
OUT2
V
OUT1
:
Output voltage when V
IN
is 24 V
V
OUT2
:
Output voltage when V
IN
is (V
OUT
+
1) V
4. Hysteresis width (V
HYS
)
V
HYS
=
(
+
V
DET
)
−
(
−
V
DET
)
+
V
DET
: Release voltage
−
V
DET
: Detection voltage
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P45
P46-P48
P49-P51
P52-P53
S-8733A0EUP-APFT2G
Mfr. #:
Buy S-8733A0EUP-APFT2G
Manufacturer:
Description:
Supervisory Circuits Combo Voltage Detec/ Voltage Reg, 8uA Iq
Lifecycle:
New from this manufacturer.
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